Semiconductor Patterning via Sequential Spacer Formation

The patent applies segmentation by dividing the patterning process into multiple stages through double-patterning and quadruple-patterning methods. Instead of attempting to create all patterns in a single lithography step, the process segments the formation of mandrels into sequential steps, where each step creates a subset of the final pattern. This allows the critical size to be reduced beyond the limits of conventional single-step lithography by breaking down the complex patterning task into manageable segments that can be achieved with current optical capabilities.

The patent employs preliminary action by pre-forming mandrel structures in a controlled sequential manner before final pattern transfer. The double-patterning and quadruple-patterning processes use preliminary spacer formation and selective etching steps that prepare the substrate in advance for subsequent patterning operations. This preliminary structuring allows for better control over the final pattern geometry and reduces the complexity of achieving high integration density, as each preliminary step is designed to create specific features that simplify later processing.

The patent applies merging by combining multiple patterning operations into integrated process flows. The double-patterning and quadruple-patterning methods merge the formation of different pattern sets into a unified sequence of spacer formation and etching steps. By merging these operations and using self-aligned approaches where spacers automatically define subsequent etch regions, the process achieves high feature resolution while minimizing the cumulative time loss that would result from completely separate patterning operations. The merging of mask layer formation and spacer processes reduces the total number of discrete steps required.