FinFET Gate Dielectric Segmentation for Leakage Prevention
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Solution Overview
Problem
In the fabrication of FinFETs with short channels, the high etching of the oxide layer leads to leakage and extrusion paths for the metal gate, complicating the process window for sequential depositions of high-k dielectric and gate layers.
Innovation Solution
A method involving the formation of a first and second dummy gate strip with different lengthwise directions, where the first dummy gate strip is removed before the second, allowing for the formation of a thinner first dielectric layer and a thicker second dielectric layer, which covers the sidewalls of spacers and exposed semiconductor fins, preventing leakage and extrusion paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high etching amount of oxide layer is performed, then process window for sequential depositions is improved, but leakage path and extrusion path for metal gate are induced
Solution Approach 1:
The patent divides the gate structure formation into multiple sequential steps with different dielectric layers (first dielectric layer 212 and second dielectric layer 220) deposited at different stages. The first dielectric layer is deposited before spacer removal, and the second dielectric layer is deposited after spacer removal, allowing each layer to serve specific functions in preventing leakage while maintaining process window.
Solution Approach 2:
The first dielectric layer 212 is deposited in advance before the spacers are removed, preparing a preliminary protective layer that prevents leakage paths during subsequent processing steps. This preliminary action ensures that when high etching is performed later, the leakage prevention is already in place.
2Manufacturing precision
If high etching amount of oxide layer is performed, then process window for sequential depositions is improved, but extrusion path for metal gate is induced
Solution Approach 1:
The patent segments the dielectric layer formation into two distinct stages: the first dielectric layer 212 deposited before spacer removal, and the second dielectric layer 220 deposited after spacer removal. This segmentation allows the second layer to specifically address extrusion path prevention while the first layer maintains process window.
Solution Approach 2:
The first dielectric layer 212 serves as a preliminary cushioning layer deposited before the high etching process. This layer provides initial protection against potential extrusion paths, and the second dielectric layer 220 is then deposited to provide additional cushioning and complete the protection against extrusion.
3Reliability
If thinner first dielectric layer and thicker second dielectric layer are formed, then leakage and extrusion paths are prevented, but device complexity increases
Solution Approach 1:
The first dielectric layer 212 and second dielectric layer 220 together serve multiple functions: they both prevent leakage paths, they both prevent extrusion paths, and they both provide electrical control. By combining these layers, the structure achieves universal protection against multiple failure modes without requiring entirely separate systems for each function.
Solution Approach 2:
The patent merges the leakage prevention function and extrusion prevention function into a unified two-layer dielectric structure. Both layers work together in sequence to provide comprehensive protection, reducing the need for separate protective measures and simplifying the overall device architecture despite the additional layer.
Data Source
AI summary
A semiconductor device including a first fin field effect transistor and a second fin field effect transistor is provided. The first fin field effect transistor includes a first semiconductor channel, a first gate overlapped with the first semiconductor channel, a first dielectric layer disposed between the first semiconductor channel and the first gate, and a pair of first spacers disposed on sidewalls of the first gate. The second fin field effect transistor includes a second semiconductor channel, a second gate overlapped with the second semiconductor channel, a second dielectric layer disposed between the second semiconductor channel and the second gate, and a pair of second spacers. The second dielectric layer further extends between the second gate and the pair of second spacers, the first dielectric layer is thinner than the second dielectric layer, and a width of the first gate is smaller than that of the second gate.