Planar Split-Gate MOSFET for Threshold Voltage Control
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Solution Overview
Problem
Conventional semiconductor power devices with planar gate structures face challenges such as uneven channel doping density, difficulty in precision control of threshold voltage, susceptibility to punch-through, and high gate-to-drain capacitance, limiting their performance in high-frequency applications and increasing production costs.
Innovation Solution
A semiconductor power device with a uniform channel dopant profile achieved through a blanket surface P-implant and angular body implant, combined with a split gate configuration, allowing for precise control of gate threshold voltage and reduced capacitance, and featuring a JFET diffusion region under the gap of the split gate to minimize on-resistance and prevent punch-through.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar gate structure is used, then manufacturing cost is reduced and foundry compatibility is improved, but channel doping density becomes uneven and threshold voltage control precision deteriorates
Solution Approach 1:
The gate is segmented into two separate gates positioned at opposite sides of the channel, rather than using a single planar gate. This segmentation allows each gate to independently control the channel doping profile, enabling precise threshold voltage control while maintaining the simplicity and low cost of planar manufacturing processes.
Solution Approach 2:
The invention introduces localized doping regions near each gate contact, creating non-uniform doping density distribution tailored to specific locations. This local quality enhancement allows precise control of threshold voltage in critical regions while maintaining overall manufacturing simplicity and compatibility with standard foundry processes.
2Device complexity
If a planar gate structure is used, then manufacturing simplicity is maintained, but the device becomes susceptible to punch-through due to sharp doping level decrease
Solution Approach 1:
The channel is divided into multiple regions with different doping densities, with higher doping levels positioned near the gate contacts and lower doping levels in the drift region. This segmentation maintains manufacturing simplicity while preventing punch-through by creating potential barriers at critical locations through the localized high-doping regions.
Solution Approach 2:
The invention changes the doping density parameter spatially, creating a graded profile that transitions from high doping near gate contacts to low doping in the drift region. This parameter variation maintains manufacturing simplicity while effectively preventing punch-through by establishing electric field barriers at strategically positioned high-doping regions.
3Device complexity
If a planar gate overlaps the drain region, then gate control is simplified, but gate-to-drain capacitance increases and limits high frequency performance
Solution Approach 1:
The single overlapping gate is segmented into two separate gates positioned at opposite sides of the channel, eliminating the direct overlap between gate and drain regions. This segmentation maintains gate control simplicity while dramatically reducing gate-to-drain capacitance, thereby enabling high-frequency operation.
Solution Approach 2:
The gate structure is extracted from the conventional overlapping configuration and repositioned to lie adjacent to the channel rather than directly over the drain region. This extraction eliminates the parasitic capacitance between gate and drain while preserving the essential gate control function through the segmented dual-gate architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a semiconductor power device with stable and precisely controllable threshold voltage, reduced capacitance, and low on-resistance, enabling high-performance operation at both high and low biases while maintaining compatibility with multiple foundries and reducing production costs.
Implementation Method 1
a blanket surface P-implant and angular body implant
Implementation Method 2
a JFET diffusion region under the gap of the split gate to minimize on-resistance and prevent punch-through
Data Source
AI summary
This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.