Selective Local Interconnect to Gate in Self Aligned Process
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Solution Overview
Problem
Current semiconductor processes for forming transistors face challenges in achieving self-aligned local interconnects to gates at 15 nm technology nodes, requiring multiple mask steps and leading to potential shorts and increased area penalties, while existing methods struggle with unidirectional metal layer issues and limited design flexibility for local interconnect routing.
Innovation Solution
A semiconductor device fabrication process that selectively removes a hard mask in specific regions over the gate using a CAD-designed resist pattern, allowing for the deposition of conductive material through insulating layers to form local interconnects, enabling routing over the gate without connecting to it, thus avoiding shorts and maintaining manufacturable metal tip-to-tip spacing without area penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-aligned contact to gate flow is used at 15 nm technology, then contact to gate shorts are avoided and channel length scaling is enabled, but additional mask steps are required due to resolution constraints
Solution Approach 1:
The local interconnect routing is segmented into two distinct categories: routes that connect to the gate and routes that pass over the gate without connecting. This is achieved through selective hard mask removal in specific regions, allowing the routing layer to be decomposed into functional segments that can be independently controlled
Solution Approach 2:
Different regions over the gate are given different properties through selective hard mask removal. In some regions, the hard mask is removed to allow gate connection, while in other regions, the hard mask remains to prevent connection. This local differentiation enables selective connectivity without requiring additional mask steps
2Productivity
If local interconnect routes are allowed to pass over the gate without connection, then routing density is improved, but gate to local interconnect shorts or leakage may occur
Solution Approach 1:
The hard mask is selectively removed in advance in regions where local interconnect routes should pass over the gate without connecting. This preliminary action establishes the connectivity pattern before the local interconnect layer is formed, ensuring that routes can pass over the gate safely without creating shorts or leakage
3Reliability
If metal layer is made unidirectional to avoid SIT issues, then manufacturing reliability is improved, but metal tip to tip spacing to neighboring cell increases causing area penalty
Solution Approach 1:
The metal layer is allowed to route in multiple directions by utilizing the vertical dimension through selective hard mask removal. Local interconnect routes can pass over the gate in regions where the hard mask has been removed, enabling bidirectional routing patterns without violating SIT constraints, thereby reducing metal tip to tip spacing and eliminating area penalties
Data Source
AI summary
A semiconductor device fabrication process includes forming a gate of a transistor on a semiconductor substrate using a hard mask. The hard mask is selectively removed in one or more selected regions over the gate. The removal of the hard mask in the selected regions allows the gate to be connected to an upper metal layer through at least one insulating layer located substantially over the transistor. Conductive material is deposited in one or more trenches formed through the at least one insulating layer. The conductive material forms a local interconnect to the gate in at least one of the selected regions.