Two-Step Sputter Etch for Copper Interconnect Liner Coverage
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Solution Overview
Problem
Conventional damascene processing for copper interconnects in integrated circuits faces challenges with smaller feature sizes, leading to poor liner/seed coverage, pinch-off, reentrant reactive ion etching profiles, voids, defects, and increased resistivity due to issues with liner thickness and copper grain size, affecting IC performance.
Innovation Solution
A two-step sputter etch process using chlorine-based or sulfur fluoride-based plasma followed by a fluorocarbon-based plasma to control the hard mask profile and pattern copper conductive lines, ensuring better adhesion and reducing defects in copper interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional damascene processing is used with smaller feature sizes, then copper interconnect lines can be made narrower, but liner/seed coverage deteriorates and defects increase
Solution Approach 1:
The etch process is segmented into two distinct steps: a first sputter etch step that creates an initial profile, and a second sputter etch step that refines the profile. This segmentation allows each step to be optimized for different aspects of the etching process, improving overall precision and liner coverage while enabling smaller feature sizes
Solution Approach 2:
The patent changes etch process parameters by using sputter etching instead of conventional reactive ion etching, and by adjusting plasma chemistry (using CF4 and CO mixtures). These parameter changes optimize the etch profile and adhesion properties, enabling better liner coverage at smaller dimensions
2Length of moving object
If conventional damascene processing is used with smaller feature sizes, then copper interconnect lines can be made narrower, but manufacturing defects increase
Solution Approach 1:
The two-step sputter etch process segments the material removal into controlled stages, with the first step removing excess hard mask and the second step creating the final precise profile. This segmentation reduces defects by preventing pinch-off and ensuring uniform copper deposition throughout the trench
Solution Approach 2:
The hard mask layer serves as an intermediary that is selectively removed through the two-step sputter etch process. This intermediary approach allows precise control over the etch profile and prevents direct damage to the copper liner, reducing defects while enabling smaller features
3Reliability
If liner thickness is increased to improve coverage, then adhesion improves, but copper grain size decreases and resistivity increases
Solution Approach 1:
The patent optimizes the etch process parameters (plasma chemistry, power, pressure) to create profiles that allow adequate liner thickness for adhesion while maintaining sufficient copper cross-section. The sputter etch process parameters are tuned to achieve the right balance between liner coverage and copper grain structure
Solution Approach 2:
The two-step etch process creates different local conditions: the first step establishes overall profile geometry for adhesion, while the second step refines the opening for optimal copper deposition. This local quality control ensures both good liner adhesion and acceptable copper grain size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved control over hard mask profiles and copper patterning, reducing defects and increasing the reliability of copper interconnects with smaller feature sizes, enhancing IC performance by maintaining better adhesion and reducing resistivity.
Implementation Method 1
performing a first sputter etch of first hard mask layer using a chlorine-based plasma, and performing a second sputter etch of first hard mask layer using a second plasma
Implementation Method 2
performing a first sputter etch of first hard mask layer using a chlorine-based plasma
Data Source
AI summary
A method for fabricating one or more conductive lines in an integrated circuit includes providing a layer of copper containing conductive metal in a multi-layer structure fabricated upon a wafer, providing a first hard mask layer over the layer of copper containing conductive metal, performing a first sputter etch of first hard mask layer using a chlorine-based plasma or a sulfur fluoride-based plasma, and performing a second sputter etch of first hard mask layer using a second plasma, wherein a portion of the layer of copper containing conductive metal residing below a portion of the first hard mask layer that remains after the second sputter etch forms the one or more conductive lines. In one embodiment, the second plasma is a fluorocarbon-based plasma.