CMOS GIDL Reduction via Intermediary Voltage Control
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Solution Overview
Problem
Gate-induced drain leakage (GIDL) in complementary metal-oxide-semiconductors (CMOS) devices leads to unnecessary electrical power consumption as the voltage difference between the gate and drain increases, causing significant leakage currents.
Innovation Solution
A protecting circuit is designed with PMOS and NMOS transistors, along with inverters, to reduce the voltage difference between the gate and drain by utilizing multiple voltage nodes, where the ground node provides a ground voltage and higher voltage nodes provide first and second voltages, both greater than the ground voltage, thereby mitigating GIDL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the voltage difference between gate and drain is increased to improve transistor switching performance, then switching speed is improved, but gate-induced drain leakage (GIDL) increases causing higher power consumption
Solution Approach 1:
The patent introduces a protecting circuit with PMOS and NMOS transistors configured as intermediaries between the input signal and the main transistor gate. This protecting circuit mediates the voltage applied to the gate, ensuring that the voltage difference between gate and drain is controlled and limited, thereby reducing GIDL while still allowing sufficient voltage for proper transistor switching operation
Solution Approach 2:
The patent changes the voltage parameter applied to the transistor gate by using a protecting circuit that limits the maximum voltage difference between gate and drain. The protecting circuit modifies the voltage waveform to prevent excessive voltage differences that cause GIDL, while maintaining adequate voltage levels for proper switching operation
2Use of energy by moving object
If the voltage difference between gate and drain is reduced to decrease GIDL, then power consumption is reduced, but transistor switching capability deteriorates
Solution Approach 1:
The protecting circuit acts as an intermediary that selectively limits voltage differences only when they would cause excessive GIDL, while still allowing adequate voltage differences for proper transistor switching. The circuit mediates between the input signal and the transistor gate to maintain optimal operating conditions
Solution Approach 2:
The patent applies different voltage control strategies to different parts of the circuit. The protecting circuit is specifically applied at the gate terminal where voltage control is needed to prevent GIDL, while other parts of the circuit maintain normal operating voltages for optimal performance
Data Source
AI summary
A protecting circuit for reducing leakage currents comprises a first PMOS transistor (P-channel Metal-Oxide-Semiconductor Field-Effect Transistor), a second PMOS transistor, a first NMOS transistor (N-channel Metal-Oxide-Semiconductor Field-Effect Transistor), and a second NMOS transistor. The first PMOS transistor is coupled between a first voltage node and a node, and comprises a first gate coupled an input node. The second PMOS transistor is coupled between the node and an output node. The first NMOS transistor is coupled between the output node and a ground node, and comprises a third gate coupled to the input node. The second NMOS transistor is coupled between the input node and a second gate of the second PMOS transistor, and comprises a fourth gate coupled to a second voltage node.