CMOS Image Sensor Isolation Region Design
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Solution Overview
Problem
Conventional CMOS image sensors face challenges in completely isolating the epitaxial layer of the pixel array from the peripheral region, leading to leakage current and noise issues.
Innovation Solution
An image sensor design with a pixel array and a peripheral region, where an isolation region is formed between and under the peripheral region to electrically isolate the pixel array from the peripheral region, using ion implantation to create red, green, and first plug isolation regions, and a second isolation region to enhance electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional isolation method is used between pixel array and peripheral region, then the structure is simple, but electrical isolation is insufficient leading to leakage current and noise
Solution Approach 1:
The isolation region is divided into multiple segments: a first isolation region formed between the pixel array and peripheral region, and a second isolation region formed under the peripheral region. This segmentation provides enhanced electrical isolation through multiple isolated zones, preventing leakage current and noise while maintaining structural organization.
Solution Approach 2:
The isolation structure extends into the vertical dimension by forming the second isolation region under the peripheral region, not just laterally between regions. This multi-level isolation approach in three-dimensional space achieves superior electrical isolation compared to conventional single-plane isolation methods.
2Reliability
If the epitaxial layer is shared between pixel array and peripheral region, then manufacturing is simpler, but leakage current affects performance
Solution Approach 1:
The epitaxial layer formation process is segmented into region-specific steps: a first epitaxial layer is formed in the pixel array region with specific properties, and a second epitaxial layer is formed in the peripheral region. This segmentation allows optimization of each region's electrical characteristics while maintaining overall manufacturing feasibility.
Solution Approach 2:
Different epitaxial layers are formed with different properties tailored to their specific functions: the first epitaxial layer in the pixel array region is optimized for light detection, while the second epitaxial layer in the peripheral region is optimized for logic circuit operation. This local quality differentiation improves signal quality without excessive manufacturing complexity.
3Reliability
If isolation region is formed only between regions, then process is simpler, but noise isolation is insufficient
Solution Approach 1:
The isolation process is segmented into two distinct formation steps: forming the first isolation region between the pixel array and peripheral region, and forming the second isolation region under the peripheral region. This segmented approach provides comprehensive noise isolation from both lateral and vertical directions.
Solution Approach 2:
The isolation structure is extended to the vertical dimension by forming the second isolation region beneath the peripheral region, creating a multi-layer isolation architecture. This three-dimensional isolation provides superior noise reduction compared to conventional two-dimensional isolation between regions only.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves electrical isolation, reducing leakage and noise, and enhances the performance, yield, and reliability of the image sensor by reducing substrate resistances of NMOS and PMOS transistors.
Implementation Method 1
using ion implantation to create red, green, and first plug isolation regions, and a second isolation region to enhance electrical isolation
Data Source
AI summary
An image sensor includes a pixel array including a photodiode, a peripheral region including a logic circuit, and an isolation region formed between the pixel array and the peripheral region and formed under the peripheral region to electrically isolate the pixel array from the peripheral region.