Selective Silicide Formation in CMOS Image Sensors
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Solution Overview
Problem
Conventional silicide formation processes in CMOS image sensors increase leakage current, degrading image quality and are difficult to control, especially in photo-sensing regions, leading to inconsistent silicide growth and reduced production yield.
Innovation Solution
A method for selective silicide formation involving the creation of isolation regions, well formation, deposition of gate and metal layers, spacer formation, ion implantation, and thermal treatments to control silicide formation in specific areas, preventing unwanted silicide growth in photo-sensing regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional silicide formation process is used in CMOS image sensor, then RC delay is improved, but leakage current increases and image quality degrades
Solution Approach 1:
The patent applies different treatments to different regions: silicide is formed in the periphery region to improve RC delay, while the photo-sensing region is protected from silicide formation to prevent leakage current. This spatial differentiation of material properties resolves the contradiction between speed improvement and harmful leakage current generation.
Solution Approach 2:
The substrate is divided into distinct regions (photo-sensing region and periphery region) with different silicide formation characteristics. By segmenting the device structure and applying region-specific processing, the patent achieves both low leakage in photo-sensing areas and fast switching in periphery areas.
2Manufacturing precision
If photo process silicide block technique is used, then selective silicide growth control is attempted, but alignment accuracy is insufficient and consistent control is not achieved
Solution Approach 1:
A silicide block layer is introduced as an intermediary material to prevent silicide formation in the photo-sensing region. This block layer serves as a physical barrier that reliably controls silicide growth location without relying on photolithographic alignment, thereby achieving consistent selective silicide formation.
Solution Approach 2:
The patent replaces the photo process-based silicide block technique with a thermal-based approach. By using thermal treatment after depositing the silicide block layer, the method achieves more reliable and consistent silicide formation control without the alignment limitations of photolithography.
3Manufacturing precision
If etch back process is used to remove silicide from source/drain regions, then selective silicide on gate is achieved, but process control is difficult and production yield reduces
Solution Approach 1:
Instead of removing silicide after formation, the patent prevents silicide formation in unwanted areas beforehand by depositing a silicide block layer in the photo-sensing region before the silicide formation step. This preliminary protective action eliminates the need for subsequent etch back processes, improving both control and yield.
Solution Approach 2:
The patent converts the potential harm of unwanted silicide formation into a benefit by using the silicide block layer as a protective measure. The block layer, which initially seems to add process complexity, actually simplifies the overall process by eliminating the need for difficult-to-control etch back operations and improving production yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves device performance by reducing leakage current and increasing yield by allowing precise control over silicide formation, ensuring high image quality and efficient production.
Implementation Method 1
The substrate is exposed to a thermal environment to form silicide in the at least two doped regions in the first well and the at least one gate in the photo-sensing region
Implementation Method 2
At least two doped regions in the first well are formed by implanting a first plurality of ions. A second plurality of ions are implanted to form a doped region in the second well
Implementation Method 3
Residual second metal layer is removed by etching
Data Source
AI summary
Techniques for manufacturing a CMOS image sensor are provided. A semiconductor substrate is provided, and at least one isolation region can be formed between a periphery region of the substrate and a photo-sensing region of the substrate. A first well in the periphery region and a second well in the photo-sensing region of the substrate are formed. A third well associated with a photodiode is also formed. A gate oxide layer, polysilicon layer, and first metal layer are respectively deposited. The polysilicon layer and first metal layer are etched to form an least one gate in the photo-sensing region and at least one gate in the periphery region. At least two doped regions in the first well are formed, as well as a doped region in the second well. A silicide block layer is deposited over the photo-sensing region of the substrate. A second metal layer is deposited at least over the periphery region after deposition of the silicide block. The substrate is exposed to a thermal environment to form silicide. The second metal layer is removed by etching.