Solid-State Devices TRIZ Cases

Centrifugal spinning and vacuum bonding eliminate voids in epoxy layers, reducing mechanical stress during thermal cycling.

A segmented hole transporting layer structure with differentiated mobility zones controls charge transport in organic light emitting displays.

A transistor uses a reentrant profile in the second conductive layer to enable conformal coating and consistent thickness.

A gate last replacement process forms high-k dielectric and metal gates for logic transistors alongside non-volatile memory cells.

Optimized porosity and thickness balance gas absorption with minimal optical attenuation.

Deposits organic materials with matched phase transition temperatures to form a uniform intermediate layer in display apparatuses.

Segmenting gate lines into spatially separated segments reduces RC delay, ensuring sufficient pixel voltage charging and preventing disconnection defects.

A white organic light emitting diode uses a three emission region structure with optimized host materials to enhance emission intensity.

T-shaped electrodes with Au-filled grooves extend humid air paths to prevent oxidation and improve heat dissipation.

Curable acrylate and quantum dot composition overcomes insufficient heat resistance and UV stability in optical devices.

Vertical metal layer stacking reduces component distances, overcoming process limits on lateral spacing to achieve higher display resolution.

An intermediate layer blocks dopant diffusion from carrier transport layers into perovskite, maintaining conversion efficiency above 90% after 1000 hours.

A concave convex upper insulation layer increases contact area between the sealant and substrate to enhance adhesion strength.

Recessing the second conductive line into an insulating layer groove eliminates step differences that cause pixel electrode protrusions and color deviation.

A common line with lower potential isolates leakage current from data lines, ensuring accurate image pickup without static interference.

Angled implants in GaN fin structures enlarge the Schottky diode cross-sectional area, resolving 2DEG saturation limits for effective ESD protection.

A semiconductor isolation region formed by combining boron and phosphorus impurity diffusion steps.

OLED panels integrate capacitive sensing to measure touch intensity without adding complex external hardware.

A photosensitive unit occupies light-emitting layer absent regions within an array substrate to generate electrical signals from sensed light intensity.

Narrow vertical side wall active pins formed from programmable resistive material enable low power phase change memory cells.

A flexible display panel integrates upper and lower resistive force-sensitive electrodes positioned relative to the neutral plane of its stacked structure.

Laminating high and low mobility active layers in a single transistor suppresses leakage current while maintaining reliability.

A non-volatile memory array uses sub-F word lines and dielectric fill to reduce cell pitch.

Embedded input-output terminals on modular analog tiles connect via an interconnect layer, eliminating wire bond parasitics and shortening development time.

Separate additive supply in wet etching controls silicon concentration to suppress abnormal oxide growth during semiconductor fabrication.

An open cavity design with an air vent reduces coefficient of thermal expansion mismatch stress, preventing warping and failure in high-stress automotive applications.

A multi-device OLED uses electrical connectors through stack openings to supply current directly to exposed electrode contact regions.

Epitaxial growth of a silicon germanium layer on crystalline silicon establishes the channel structure for pFET devices.

Raised shallow trench isolation structures define self-aligned contact holes, eliminating gate misalignment risks and reducing manufacturing costs.

A non-volatile memory cell uses a recess trench to extend the channel vertically, creating a three-dimensional charge-trapping structure.

Dual-layer electrodes with H2O-assisted etching narrow widths, increasing aperture ratio while reducing light reflectance.

A SOI substrate uses a deuterium and hydrogen co-doped layer to reduce parasitic capacitance.

Distinct electrode structures enable four resistance levels in phase-change random access memories, resolving precision challenges for higher density.

Aluminum electrode ionizes to penetrate silicon resistive layer, stabilizing conductive filaments for improved data retention.

A method uses a sulfur exfoliation layer to peel off organic light emitting layers during heating, enabling precise mask alignment.

A touch sensor integrates color control layers on an OLED encapsulation substrate to enable full-color display without separate filters.

Segmented inspection tool measures axial or radial clearance in helicopter pitch change links without complete removal, reducing downtime.

Electrostatic spray deposition selectively deposits organic material onto sub-pixel regions using a potential difference, eliminating mask shadow effects.

A refraction inducing layer with convex and concave parts redirects light within an OLED stack to enhance extraction efficiency.

Co-depositing organoaminosilane and organoaminohafnium precursors achieves homogeneous silicon doping in hafnium oxide for ferroelectric memory devices.

Specific substituents on a multiple resonance core enable narrow blue emission, avoiding the wavelength shift caused by expanding conjugated systems.

A magnetic memory device uses a single-layer ferromagnetic pinned pattern to stabilize magnetization and reduce surface roughness.

A semiconductor device uses a dummy buffer stack structure with conductive rings to form peripheral contact plugs.

A qubit readout system uses a low-loss infrared filter to block infrared radiation and maintain high fidelity measurements.

Selective silicide formation prevents leakage current in photo-sensing regions by blocking unwanted metal reactions.

Adjustable sensor layer thickness tunes the energy band gap for visible light detection.

A semiconductor light emitting device uses a metal layer to dissipate heat from the stacked body and wavelength conversion layer.

A liquid crystal display device uses a dual link structure to reduce bezel width.