Semiconductor Isolation Region Lateral Diffusion Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for forming isolation regions in semiconductor integrated circuits using thermal diffusion of impurities result in lateral diffusion, making it difficult to reduce the size of the semiconductor integrated circuit due to the large pattern area required.
Innovation Solution
A method involving the formation of a semiconductor device with a semiconductor substrate of a first general conductivity type, a semiconductor layer of a second general conductivity type, and an isolation region formed by introducing impurities of both types, where the impurities are thermally diffused to create a combined isolation region with a smaller width at the upper and lower ends compared to the center, using boron and phosphorus impurities to suppress lateral extension.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impurities are introduced into the semiconductor substrate and thermally diffused to form an isolation region, then the isolation region can be formed, but lateral diffusion occurs causing the isolation region and well region to require a large pattern area
Solution Approach 1:
The isolation region formation process is segmented into multiple steps: first forming an isolation region in the semiconductor substrate, then forming another isolation region in the semiconductor layer, and finally combining them. This segmentation allows control over lateral diffusion at each stage, reducing the overall pattern area required.
Solution Approach 2:
The method performs preliminary action by first forming an isolation region in the semiconductor substrate before forming the semiconductor layer and additional isolation regions. This preliminary isolation region serves as a foundation that constrains subsequent lateral diffusion, reducing the pattern area needed for the final isolation structure.
2Reliability
If impurities are thermally diffused to form isolation regions, then electrical isolation can be achieved, but the lateral diffusion increases the size of the semiconductor integrated circuit
Solution Approach 1:
The method applies local quality by introducing different types of impurities (first type and second type) into specific regions of the semiconductor layer. The first impurity region and second impurity region are formed with different conductivity types, creating localized electrical properties that achieve isolation while controlling lateral diffusion boundaries.
Solution Approach 2:
The isolation structure uses composite materials by combining impurities of the first general conductivity type and impurities of the second general conductivity type in adjacent regions. This composite approach creates an isolation region with controlled electrical properties that achieves effective isolation while minimizing lateral extension.
3Ease of manufacture
If a conventional isolation region is formed using single-type impurity diffusion, then the process is simple, but the isolation region has uniform width requiring large pattern area
Solution Approach 1:
The method applies local quality by introducing different types of impurities (first type and second type) into specific regions of the semiconductor layer. The first impurity region and second impurity region are formed with different conductivity types, creating localized electrical properties that achieve isolation while controlling lateral diffusion boundaries.
Solution Approach 2:
The isolation region develops a non-uniform width profile with smaller width at the upper end and lower end compared to the center, creating a curved or tapered geometry. This shape reduces the pattern area required while maintaining effective isolation, as the narrower ends minimize the footprint without compromising the isolation function in the center region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the pattern area of the isolation region and the overall size of the semiconductor integrated circuit by controlling the diffusion of impurities, allowing for a more compact design while avoiding interference with other diffusion layers.
Implementation Method 1
thermally diffusing the impurities in the first impurity region and the impurities in the second impurity region to form an upper isolation region
Data Source
AI summary
A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an isolation region when impurities are thermally diffused in a semiconductor substrate to form the isolation region. Boron ions (B+) are implanted into an epitaxial layer through a third opening K3 to form a P-type impurity region, using a third photoresist as a mask. Then a fourth photoresist is formed on a silicon oxide film to have fourth openings K4 (phosphorus ion implantation regions) that partially overlap the P-type impurity region. Phosphorus ions (P+) are implanted into the surface of the epitaxial layer in etched-off regions using the fourth photoresist as a mask to form N-type impurity regions that are adjacent the P-type impurity region. After that, a P-type upper isolation region is formed in the epitaxial layer by thermal diffusion so that the upper isolation region and a lower isolation region are combined together to make an isolation region.