Gate Last Replacement for NVM and Logic Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in efficiently integrating non-volatile memory (NVM) cells with metal gate/high-k dielectric logic transistors on the same integrated circuit, requiring numerous additional steps and precise alignment, which complicates the integration of NVM with CMOS logic circuitry.
Innovation Solution
A method involving a gate last replacement process to form high-k dielectric and metal gates for both logic and select gate stacks, allowing flexibility in material choices and simplifying the integration by using a high-k first metal gate last replacement process, where the select gate can remain polysilicon, thereby streamlining the integration of NVM and logic transistors on a single integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional separate process integration methods are used for NVM and CMOS logic, then each transistor type can be manufactured with its own optimized process, but the number of additional process steps increases and manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of control gates and select gates into a single integrated process sequence. The control gate is formed first, then the select gate is formed in the same processing sequence using similar materials and steps, eliminating the need for separate process lines and reducing overall manufacturing complexity while maintaining optimized performance for both transistor types.
2Reliability
If metal gate/high-k dielectric structures are integrated with NVM cells, then logic transistor performance is improved, but the number of additional process steps increases
Solution Approach 1:
The control gate structure, including the high-k dielectric and metal gate layers, is formed in advance before the select gate formation begins. This preliminary action allows the complex metal gate/high-k dielectric structure to be established while the processing sequence is still in progress, rather than adding it as a final step, thereby improving manufacturing efficiency.
Solution Approach 2:
The gate formation process is segmented into distinct phases: control gate formation phase followed by select gate formation phase. This segmentation allows each gate type to be optimized independently while being manufactured in an integrated sequence, reducing the total number of additional process steps required.
3Manufacturing precision
If precise alignment is implemented for integrating NVM and logic transistors, then device performance is improved, but manufacturing complexity and process steps increase
Solution Approach 1:
The control gate structure serves as a self-aligned reference for subsequent select gate formation. By using the control gate and its associated layers as alignment markers and process references, the method achieves precise alignment automatically through the process sequence itself, rather than requiring separate alignment steps or complex positioning systems.
Data Source
AI summary
Forming a semiconductor device in an NVM region and in a logic region using a semiconductor substrate includes forming a dielectric layer and forming a first gate material layer over the dielectric layer. In the logic region, a high-k dielectric and a barrier layer are formed. A second gate material layer is formed over the barrier and the first material layer. Patterning results in gate-region fill material over the NVM region and a logic stack comprising a portion of the second gate material layer and a portion of the barrier layer in the logic region. An opening in the gate-region fill material leaves a select gate formed from a portion of the gate-region fill material adjacent to the opening. A control gate is formed in the opening over a charge storage layer. The portion of the second gate material layer is replaced with a metallic logic gate.