Modular Analog IC Interconnect Layer Reduces Parasitics
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Solution Overview
Problem
Traditional integrated circuit (IC) design and layout face challenges such as parasitic resistance, capacitance, and inductance issues due to internal routing and wire bond connections, leading to space inefficiency and high development costs, as well as limitations in reconfigurability and flexibility for creating new products or derivative products.
Innovation Solution
A modular design approach using standardized, programmable tiles with embedded I/O terminals and interconnect layers, allowing for flexible reconfiguration and reduced parasitics, enabling quicker development and implementation of high-performance, application-specific ICs without the need for extensive re-layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional internal routing and wire bond connections are used, then I/O terminals can be connected to functional blocks, but parasitic resistance, capacitance, and inductance increase
Solution Approach 1:
The patent extracts the harmful wire bond connections and external package leads from the IC structure, integrating I/O terminals directly into the semiconductor die. This eliminates the external parasitic elements (wire bonds, package leads) that cause resistance, capacitance, and inductance, while maintaining the essential connection function between I/O terminals and functional blocks through internal routing only.
Solution Approach 2:
The patent redistributes I/O terminals across multiple metal layers in three-dimensional space rather than confining them to a single planar layer. This vertical dimensionality allows I/O terminals to be positioned closer to functional blocks while avoiding planar routing constraints, thereby reducing parasitic inductance and resistance without increasing die area.
2Ease of operation
If wire bonds and package pins are used for packaging, then I/O terminals can be connected to PCB, but space is wasted
Solution Approach 1:
The patent removes the external package structure (package body, leads, wire bonds) from the traditional IC assembly, exposing I/O terminals directly on the die surface. This extraction eliminates the space-consuming package components while preserving the essential function of connecting to PCB through solder bumps or wire bonds directly to the exposed terminals.
Solution Approach 2:
The patent designs I/O terminals with universal functionality that can serve multiple purposes: they can be directly soldered to PCB, connected via wire bonds, or configured for other packaging methods. This multi-functionality eliminates the need for dedicated package leads and bond pads, reducing the overall area required for I/O connections.
3Adaptability or versatility
If functional blocks are added or removed to create new products, then product versatility improves, but re-layout time and cost increase
Solution Approach 1:
The patent segments the IC into modular functional blocks that can be independently selected and configured. Each functional block has standardized interfaces and can be added or removed without affecting the overall layout structure, enabling rapid product customization through software configuration rather than physical re-layout.
Solution Approach 2:
The patent implements dynamic configurability where the IC's functional configuration can be changed after manufacturing through software programming or configuration registers. This allows the same physical die to serve multiple product variants without requiring re-layout or re-manufacturing, significantly reducing development time and cost for new products.
4Adaptability or versatility
If functional blocks are disabled or deleted to modify existing products, then new product creation is enabled, but circuitry space is wasted or re-layout resources are consumed
Solution Approach 1:
The patent incorporates optional functional blocks and routing paths during the initial design and manufacturing process, even though they may not be used in all product variants. These preliminary-configured elements can be easily disabled through software or configuration controls, avoiding the need for costly re-layout or re-manufacturing while maintaining manufacturing efficiency.
Data Source
AI summary
A method of constructing an integrated circuit involves selecting modular tiles and then generating a functional circuit layout using the tiles. Modular tiles that perform predetermined functions and that have approximately the same length and width dimensions are selected from a library of validated tiles. The tiles have input-output terminals embedded in their upper active layers. A functional circuit layout for the integrated circuit is generated using the tiles. In many implementations, the physical layout of the integrated circuit does not include the step of routing. Then an interconnect layer is added over the functional circuitry of the tiles and connects the input-output terminals to bond pads located at the perimeter of the functional circuit layout. Chip data corresponding to the functional circuit layout is generated, and then mask reticles corresponding to the chip data are generated. The integrated circuit is formed on a wafer based on the mask reticles.