Non-volatile Memory Cells with Recess Trench for Density and Reliability
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Solution Overview
Problem
The challenge in the semiconductor industry is to minimize short-channel effects, the second-bit effect, and breakdown between the source/drain and gate in localized charge-trapping dual bit memory cells, particularly as memory cells are scaled down, which affects memory density and reliability.
Innovation Solution
The solution involves creating non-volatile memory cells with extended channel dimensions and a dielectric material between the gate and source/drain regions, using a recess trench to separate the source/drain regions and forming a charge-trapping layer on the dielectric material, which helps in reducing unwanted electron injection and improving dielectric strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOSFET channel length is reduced to increase memory density, then memory density is improved, but short-channel effects increase causing threshold voltage skew and punch-through
Solution Approach 1:
The patent extends the channel length in the vertical dimension by creating a recess trench and forming the charge-trapping layer within this three-dimensional structure. This allows the effective channel length to be longer than the planar distance between source and drain, thereby reducing short-channel effects while maintaining small footprint for high density
Solution Approach 2:
The charge-trapping layer is nested within the recess trench structure, which itself is formed between the source and drain regions. This nested configuration allows the channel to extend vertically into the substrate, achieving longer effective channel length without increasing lateral dimensions
2Reliability
If source and drain depletion regions are reduced to minimize short-channel effects, then short-channel effects are reduced, but bit-line resistance increases affecting voltage-current characteristics
Solution Approach 1:
By extending the channel vertically into the recess trench, the patent reduces the lateral spread of depletion regions while maintaining sufficient channel length. This vertical extension allows better control of depletion region geometry, reducing their harmful interaction without requiring excessive reduction in source/drain dimensions
3Quantity of substance
If channel length is reduced to increase memory density, then memory density is improved, but the second-bit effect increases causing unwanted electron injection
Solution Approach 1:
The vertical extension of the channel into the recess trench increases the physical separation between storage sites for different bits. This three-dimensional arrangement reduces unwanted electron injection from one bit to another during programming operations, mitigating the second-bit effect while maintaining high density
4Quantity of substance
If memory cells are scaled down to increase density, then memory density is improved, but breakdown between source/drain and gate increases
Solution Approach 1:
By extending the channel vertically into the recess trench, the patent increases the physical distance between the source/drain regions and the gate. This vertical separation reduces the electric field strength and probability of breakdown occurring, thereby improving reliability while maintaining small lateral dimensions for high density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved performance by reducing the second-bit effect and minimizing breakdown between the source/drain and gate, thereby enhancing memory cell reliability and density without increasing overall cell size.
Implementation Method 1
The nitride layer in the ONO gate dielectric layer is able to trap electrons in a localized manner when programmed. Charge localization refers to the nitride material's ability to store the charge without much lateral movement of the charge throughout the nitride layer.
Implementation Method 2
a dielectric material disposed between the gate and a source/drain region... improving dielectric strength... minimizing breakdown between the source/drain and gate
Data Source
AI summary
Methods for forming non-volatile memory cells include: (a) providing a semiconductor substrate having at least two source/drain regions, and a dielectric material disposed on the substrate above at least one of the at least two source/drain regions wherein the dielectric material has an exposed surface, and wherein the at least two source/drain regions are separated by a recess trench having an exposed surface, wherein the trench extends downward into the substrate to a depth position below the at least two source/drain regions; (b) forming a charge-trapping layer on the exposed surfaces of the dielectric material and the recess trench; and (c) forming a gate above the charge-trapping layer.