Pixel Structure Vertical Stacking for High Resolution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current display panel technologies face limitations in reducing the area occupied by each pixel region due to constraints in process capability, which hinders the achievement of high-resolution displays.
Innovation Solution
A pixel structure is designed with a patterned semiconductor layer, gate insulating layer, metal layers, and insulating layers, where the second drain is positioned closer to the data line than the first drain, and sources are arranged to reduce distances between components, allowing for a more compact pixel layout and enhanced resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the area occupied by each pixel region is reduced to achieve high definition, then the resolution of the display panel is improved, but the distance between electrode and wire cannot be further shortened due to process capability limits
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar two-dimensional layout to a three-dimensional stacked structure. Multiple electrode layers (first electrode layer, second electrode layer, third electrode layer) are arranged vertically, allowing connections to be made in the Z-direction rather than being constrained to horizontal routing. This vertical stacking enables shorter effective distances between functional elements while maintaining larger lateral spacing required by process capabilities.
Solution Approach 2:
The patent implements nesting by placing multiple functional layers within each other vertically. The first electrode layer is positioned at a first level, the second electrode layer at a second level, and the third electrode layer at a third level, with insulating layers nested between them. This nested arrangement allows compact integration of multiple electrodes and wiring functions within a small lateral footprint while maintaining adequate spacing in the vertical dimension.
2Manufacturing precision
If multiple electrodes and wires are arranged in a compact layout to reduce pixel area, then the resolution is improved, but the manufacturing complexity increases due to multiple metal layers and insulating layers
Solution Approach 1:
The patent applies segmentation by dividing the electrode and wiring functions into separate, discrete layers. Each metal layer (first, second, and third electrode layers) is independently formed and patterned, allowing for modular manufacturing. This segmentation enables each layer to be optimized independently for its specific function while simplifying the overall fabrication process through standardized repetitive steps.
Solution Approach 2:
By moving complex interconnections to the vertical dimension through multiple stacked layers, the patent reduces the complexity of lateral routing. The vertical stacking allows direct vertical or near-vertical connections between layers, eliminating the need for complex lateral wire routing and reducing the number of lithography steps required in the planar dimension.
3Manufacturing precision
If the distance between first drain and first data line is reduced to improve resolution, then the pixel area is reduced, but the process capability limits the minimum achievable distance
Solution Approach 1:
The patent resolves the distance limitation by utilizing the vertical dimension. Instead of attempting to reduce the lateral distance between the first drain and first data line beyond process capabilities, the structure allows connections to be made through vertical stacking with insulating layers, effectively bypassing the lateral resolution limit of the fabrication process.
Solution Approach 2:
The patent introduces insulating layers as intermediary elements between conductive layers. These insulating layers enable vertical separation and electrical isolation while allowing close lateral positioning of conductive features. The insulating layers act as mediators that permit reduced pixel area by enabling three-dimensional routing rather than being constrained to two-dimensional lateral spacing.
Data Source
AI summary
A pixel structure includes a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer. The second metal layer is disposed on the first insulating layer, and the second metal layer includes at least one first data line, at least one source, and at least one first drain, wherein the first data line is electrically connected to the source. The second insulating layer is disposed on the second metal layer, the second insulating layer includes at least one opening that is disposed corresponding to the first drain, and the area of the opening is greater than the area of the first drain. The third metal layer includes at least one second drain that is electrically connected to the first drain, the second drain is disposed corresponding to the opening and disposed on the first drain.