Display Device Gate Line Segmentation for RC Delay Reduction
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Solution Overview
Problem
As liquid crystal displays increase in size and resolution, signal delays such as RC delays can occur, leading to insufficient charging of pixel voltages, which deteriorates display characteristics.
Innovation Solution
A display device structure is developed with a substrate, a first conductor, a first insulating layer thicker than the conductor, a semiconductor, and a second conductor, including source and drain electrodes, with a passivation layer and pixel electrode formed on the semiconductor, to reduce signal delays and improve display characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the display device increases in size and resolution, then the display quality is improved, but signal delay increases causing insufficient charging of pixel voltages
Solution Approach 1:
The gate line is divided into multiple segments (first gate line, second gate line, third gate line) that are spatially separated and independently connected to different transistor groups. This segmentation reduces the RC delay by shortening the effective length of each gate line segment, allowing faster voltage propagation to pixel electrodes in large high-resolution displays
Solution Approach 2:
The patent introduces a vertical dimension by stacking multiple gate lines (first, second, third gate lines) at different vertical positions. This three-dimensional arrangement allows simultaneous control of multiple transistor rows, reducing the time required to charge pixel voltages across the entire display while maintaining high resolution
2Reliability
If the first insulating layer thickness is increased to cover lateral side surfaces of the first conductor, then connection reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent specifies a particular thickness range for the first insulating layer (500-2000 nm) that is sufficient to cover the lateral side surfaces of the first conductor (gate line) and prevent disconnection, while not being excessively thick to cause manufacturing difficulties. This optimized parameter range balances reliability improvement with manufacturing feasibility
Data Source
AI summary
The present invention relates to a display device and a manufacturing method thereof. The display device includes a substrate, a first conductor disposed on the substrate, a first insulating layer disposed on the first conductor, a second insulating layer disposed on the first insulating layer, a semiconductor disposed on the second insulating layer, and a second conductor disposed on the semiconductor. A thickness of the first insulating layer is greater than a thickness of the first conductor, and the first insulating layer includes a first opening exposing the first conductor.