Sub-F Word Line Memory Array Fabrication
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Solution Overview
Problem
Existing non-volatile memory technologies, such as NROM cells, face challenges in achieving the theoretical minimum cell size due to side diffusion of bit lines, resulting in larger cell areas and reduced density in memory arrays, especially at advanced process nodes below 170 nm.
Innovation Solution
The implementation of sub-F feature size word lines and spacings filled with dielectric, combined with self-aligned polysilicon or metal word line patterning techniques, allows for the creation of denser memory arrays by reducing the cell size and increasing the number of bits per given area, achieving a double density array with cells smaller than the prior art minimum size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thermal oxide growth is used to create bit line oxides, then the oxides grow to protect bit lines, but the bit lines diffuse sideways expanding beyond the implantation area, increasing cell spacing requirements
Solution Approach 1:
The patent performs preliminary actions by depositing bit line oxides before polysilicon layer formation, and creating spacers before bit line implantation. These preliminary structures constrain subsequent diffusion processes and prevent bit line expansion beyond desired boundaries, thereby protecting against unwanted diffusion while maintaining compact cell dimensions.
Solution Approach 2:
The patent introduces spacers as intermediary structures between bit lines and polysilicon columns. These spacers act as physical barriers that mediate the interaction between bit lines and surrounding structures, preventing direct contact and unwanted diffusion while maintaining the required electrical isolation and structural integrity.
2Reliability
If bit line spacing is increased to 1.6 F to accommodate diffusion, then bit line protection is improved, but the cell area increases to 5-6 F2 beyond the theoretical minimum of 4 F2
Solution Approach 1:
The patent changes the parameters of the fabrication process by using deposited oxides instead of thermally grown oxides, and by introducing spacer structures with controlled dimensions. These parameter changes enable precise control over bit line spacing and oxidation extent, achieving adequate isolation at the theoretical minimum cell area of 4 F2 rather than requiring 5-6 F2.
3Ease of manufacture
If polysilicon columns are etched to create word line gates, then word line formation is achieved, but the polysilicon columns are consumed and cannot serve as continuous bit line structures
Solution Approach 1:
The patent segments the polysilicon structure into separate functional elements: continuous polysilicon bit line structures and discrete polysilicon word line gates. The bit lines are formed as continuous structures that remain intact, while word line gates are created as separate etched features. This segmentation allows word line patterning through selective etching without compromising the integrity of the continuous bit line structures.
Data Source
AI summary
A non-volatile memory array has word lines spaced a sub-F (sub-minimum feature size F) width apart and bit lines generally perpendicular to the word lines. The present invention also includes a method for word-line patterning of a non-volatile memory array which includes generating sub-F word lines from mask generated elements with widths of at least a minimum feature size F.