CMOS Image Sensor Triple Gate Structure for Dark Current Reduction
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Solution Overview
Problem
Conventional CMOS image sensor manufacturing techniques face challenges in reducing dark current, particularly due to defects on the silicon surface and silicon-gate oxide interface in photodiode regions, which affect sensor performance, especially under low light conditions.
Innovation Solution
A method for forming a CMOS image sensor device involves a semiconductor substrate with P-type impurity, forming dielectric layers of varying thicknesses, and creating gate structures to reduce dark current by protecting the photodiode device regions from damage and contamination, using thermal oxidation and etching processes to minimize defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing techniques are used, then manufacturing simplicity is maintained, but dark current is high due to defects on silicon surface and silicon-gate oxide interface
Solution Approach 1:
The patent divides the gate structure into multiple segments: a first gate electrode and a second gate electrode separated by a gate spacer. This segmentation allows different regions of the gate to serve different functions - the first gate controls the photodiode while the second gate controls the transfer gate, enabling independent optimization of each function to reduce dark current without overly complicating the manufacturing process
Solution Approach 2:
The patent applies local quality by creating a gate spacer only in specific regions where needed. The gate spacer is positioned between the first and second gate electrodes at the photodiode region, providing localized electrical isolation where dark current reduction is most critical, while maintaining simplicity in other regions of the device
2Productivity
If pixel density is increased, then circuit density is improved, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent introduces a vertical dimension to the gate structure by stacking the first gate electrode, gate spacer, and second gate electrode in layers. This three-dimensional arrangement allows for higher pixel density in the planar direction without requiring smaller feature sizes, as the additional vertical layering provides functional separation without lateral compression
Solution Approach 2:
The gate spacer is nested between the first and second gate electrodes, creating a compact structure where multiple functional elements are contained within a limited lateral footprint. This nesting allows the transfer gate control structure to be integrated within the pixel region without increasing overall pixel area, supporting higher pixel density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a CMOS image sensor with significantly reduced leakage current, enhancing device reliability and performance, as demonstrated by experimental results showing minimal leakage current in wafers fabricated using this method compared to conventional methods.
Implementation Method 1
forming a first thickness of silicon dioxide in a first region of the surface region, forming a second thickness of silicon dioxide in a second region of the surface region, and forming a third thickness of silicon dioxide in a third region of the surface region
Data Source
AI summary
A method of forming a CMOS image sensor device, the method includes providing a semiconductor substrate having a P-type impurity characteristic including a surface region. The method forma first thickness of silicon dioxide in a first region of the surface region, a second thickness of silicon dioxide in a second region of the surface region, and a third thickness of silicon dioxide in a third region of the surface region. The method includes forming a first gate layer overlying the second region and a second gate layer overlying the third region, while exposing a portion of the first thickness of silicon dioxide. An N-type impurity characteristic is formed within a region within a vicinity underlying the first thickness of silicon dioxide in the first region of the surface region to cause formation of a photo diode device characterized by the N-type impurity region and the P-type substrate.