CMOS I/O Driver Single-Well Charging for Over-Voltage Protection

Solution Overview

Problem

Existing I/O driver designs require complex and space-consuming charging circuitry to prevent gate oxide and well junction breakdown during over-voltage and back-drive operations, which complicates the layout and increases the risk of leakage.

Innovation Solution

A CMOS I/O driver design utilizing a cascoded pair of PMOS and NMOS transistors with a single well charging voltage method, where the wells and gates of transistors are charged to a common voltage during over-voltage and back-drive operations, reducing complexity and layout space through the use of switches and diode-connected transistors to manage voltage levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If complex charging circuitry with multiple wells and gates is used to prevent breakdown during over-voltage and back-drive operation, then protection reliability is improved, but device complexity and layout space increase

Engineering Contradiction:

Improveprotection against gate oxide and well junction breakdownVSAvoidcomplexity of charging circuitry

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the charging of multiple PMOS transistor wells into a single common well charging operation. Instead of charging each well independently to different voltage levels, the invention charges all PMOS wells to a common voltage level, thereby reducing the number of charging circuits and multiplexer arrangements while maintaining protection against well junction breakdown during over-voltage and back-drive operations.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If complex charging circuitry with multiple wells and gates is used to prevent breakdown during over-voltage and back-drive operation, then protection reliability is improved, but layout space is increased

Engineering Contradiction:

Improveprotection against gate oxide and well junction breakdownVSAvoidlayout space of charging circuitry

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the charging of multiple PMOS transistor wells into a single common well charging operation. Instead of charging each well independently to different voltage levels, the invention charges all PMOS wells to a common voltage level, thereby reducing the number of charging circuits and multiplexer arrangements while maintaining protection against well junction breakdown during over-voltage and back-drive operations.

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If complex charging circuitry with multiple wells and gates is used to prevent breakdown during over-voltage and back-drive operation, then protection reliability is improved, but leakage risk is increased

Engineering Contradiction:

Improveprotection against gate oxide and well junction breakdownVSAvoidleakage from complex charging circuitry

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent merges the charging of multiple PMOS transistor wells into a single common well charging operation. Instead of charging each well independently to different voltage levels, the invention charges all PMOS wells to a common voltage level, thereby reducing the number of charging circuits and multiplexer arrangements while maintaining protection against well junction breakdown during over-voltage and back-drive operations.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts and eliminates the complex multiplexer arrangement and multiple independent charging circuits from the design. By removing these unnecessary components and simplifying the charging architecture to a single common well charging mechanism, the invention reduces leakage paths and potential failure points while maintaining adequate protection.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS7605619B1I/O protection under over-voltage and back-drive conditions by single well charging

Publication Date: 2009.10.20 NAT SEMICON CORP

AI summary

In an I/O driver that includes a cascoded pair of PMOS driver transistors connected to a pair of cascaded NMOS driver transistors and that defines a pad output between the PMOS and NMOS driver transistors, a method of providing the CMOS I/O driver with over-voltage and back-drive protection includes providing circuitry for charging the wells of the PMOS transistors either to VDDIO during normal voltage mode by making use of the power supply, or to a common voltage during over-voltage and back-drive operation using the pad voltage.