Reliability Increase In Field Effect Transistors TRIZ Cases
- CMOS I/O Driver Single-Well Charging for Over-Voltage Protection
Single-well charging lets CMOS I/O drivers use pad voltage during back-drive and over-voltage events, cutting circuit area, complexity, and leakage.
- CMOS Switch Topology to Prevent NBTI Damage in PMOS Pairs
A CMOS switch uses shunting PMOS pairs and ground decoupling to prevent NBTI damage, preserve threshold matching, and reduce duty cycle distortion.
- USB 2.0 Transmitter Cascode Output Stage for 2.5V CMOS
A cascode 3.3V USB output stage lets standard 2.5V CMOS devices meet signal levels while limiting stress and blocking 5V short damage.
- Latch Circuit Topology That Blocks Stationary Soft Errors
Same-phase inputs trigger positive feedback only in sync, preventing stationary soft errors while keeping latch area low and response speed intact.
- Protection Circuit Using Segmented MOSFETs for Reverse Polarity
A protection circuit isolates reverse bias control from high current paths using segmented P-channel MOSFETs.
- Single Event Latch-Up Protection Circuit With Delayed Power Removal
A single event latch-up detection circuit senses load current and controls a field effect transistor switch to manage power delivery.
- Output Driver Overvoltage Protection via Fractional Supply
A power conditioner generates a fractional pad voltage to protect output driver transistors from overstress.
- Trigger Circuit Transient Immunity via State-Dependent Capacitance
A trigger circuit detects transient voltage increases and controls a clamping device using a common capacitive element to prevent voltage rail collapse.