Latch Circuit Topology That Blocks Stationary Soft Errors

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing semiconductor latch circuits face challenges in minimizing area occupation and maintaining response speed while enhancing soft error resistance, as existing methods either increase circuit complexity or fail to prevent stationary errors due to soft errors.

Innovation Solution

A latch circuit design incorporating a feedback circuit with multiple inverter stages that applies positive feedback only when input signals of the same phase are simultaneously input, using a predetermined number of amplification stages to reduce the likelihood of stationary errors and maintain response speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple dynamic latches are prepared with independent feedback loops to increase soft error resistance, then soft error resistance improves, but circuit area increases and response speed decreases

Engineering Contradiction:

Improvesoft error resistanceVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple feedback loops into a single shared feedback path. Instead of preparing multiple independent dynamic latches with separate feedback loops, the invention uses one feedback loop that is shared among multiple latches, thereby reducing circuit area while maintaining soft error resistance through the differential structure

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The feedback loop serves multiple functions simultaneously: it provides feedback for multiple latches (multi-functionality) while also implementing soft error resistance through the differential comparison mechanism. The single feedback loop structure is universally applied to all latches in the circuit

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If multiple dynamic latches are prepared with independent feedback loops to increase soft error resistance, then soft error resistance improves, but response speed decreases

Engineering Contradiction:

Improvesoft error resistanceVSAvoidresponse speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

By merging multiple feedback loops into a single shared feedback path, the patent reduces the total number of feedback operations required. This consolidation decreases the cumulative feedback time across all latches, thereby improving overall response speed while maintaining soft error resistance

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If parity check circuitry is added to obtain parity between output signals to prevent soft errors, then soft error resistance improves, but circuit complexity and area increase

Engineering Contradiction:

Improvesoft error resistanceVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the error detection function from separate parity check circuitry and integrates it directly into the feedback loop structure. The differential latch inherently compares signals and detects errors through its feedback mechanism, eliminating the need for separate parity check circuits

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The error detection and correction functions are merged with the feedback mechanism. The feedback loop simultaneously performs signal regeneration and error detection through differential comparison, reducing overall circuit complexity

Inventive Principle:

Principle #5Merging (Combining)

4Quantity of substance

If charge capacities of storage nodes are reduced to achieve high integration, then integration density improves, but soft error resistance decreases

Engineering Contradiction:

Improveintegration densityVSAvoidsoft error resistance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies different characteristics to different parts of the storage structure. The differential latch structure creates local redundancy where each latch's state is represented by two complementary nodes, providing inherent error resistance even with reduced charge capacity per node

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The differential latch uses asymmetric signal paths with different numbers of inverter stages (odd number for one path, even number for the other), creating inherent signal differentiation that improves soft error resistance while allowing reduced charge capacity

Inventive Principle:

Principle #4Asymmetry

Data Source

PatentUS7474116B2Latch circuit

Publication Date: 2009.01.06 SOCIONEXT INC

AI summary

A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.