USB 2.0 Transmitter Cascode Output Stage for 2.5V CMOS

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Solution Overview

Problem

Conventional USB transmitters using 3.3V devices are not portable in leading edge CMOS fabrication processes and replacing them with 2.5V devices subjects transistors to stress, increasing production costs and risk of damage during 5V short conditions.

Innovation Solution

A 3.3V output stage design utilizing a cascode approach with modified pullup/pulldown signal levels and cascode biasing that maintains transistor potentials at 2.5V or less, using standard 2.5V transistors and shutting off the pullup path during 5V short conditions to prevent damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If 3.3V devices are used in USB transmitters, then the output signal level requirement is met, but the devices are not portable in leading edge CMOS fabrication processes and add production costs

Engineering Contradiction:
Improveoutput signal levelVSAvoidfabrication process compatibility
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent changes the voltage parameter from 3.3V to 2.5V by introducing cascode transistors that transform the output voltage level while allowing the use of standard 2.5V CMOS devices in leading edge fabrication processes, thus resolving the contradiction between meeting output signal requirements and fabrication process compatibility

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If 2.5V devices replace 3.3V devices, then fabrication process compatibility is improved, but transistors are subjected to stress and risk of damage during 5V short conditions

Engineering Contradiction:
Improvefabrication process compatibilityVSAvoidtransistor stress resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The cascode transistors serve as intermediary elements between the 2.5V devices and the 5V potential, limiting the voltage across the 2.5V transistors to safe levels even during 5V short conditions, thus protecting the devices while maintaining fabrication process compatibility

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The cascode configuration provides beforehand protection by structurally limiting the maximum voltage that can appear across the 2.5V transistors, cushioning them against stress and potential damage before such conditions occur

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Ease of manufacture

If 2.5V devices are used without cascode protection, then production costs are reduced, but accurate models accounting for device degradation are required

Engineering Contradiction:
Improveproduction costVSAvoidmodeling complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The cascode transistors act as protective intermediaries that eliminate the need for complex degradation models by physically preventing excessive voltage stress on the 2.5V devices, thus reducing both production costs and modeling complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7521966B2USB 2.0 transmitter using only 2.5 volt CMOS devices
Publication Date: 2009.04.21 SYNOPSYS INC
  • US7521966B2 patent drawing
  • US7521966B2 patent drawing
  • US7521966B2 patent drawing

AI summary

A USB transmitter 3.3V output stage includes a PMOS cascode transistor connected between a PMOS pullup transistor and a USB port data pin, an NMOS cascode transistor connected between an NMOS pulldown transistor and the data pin, and an output driver circuit that generates a pullup signal range of 0.8V to 3.3V, and a pulldown signal range of 0V to 2.5V, whereby the pullup and pulldown transistors are subjected to 2.5V gate-to-source potentials. A protection/bias circuit biases the PMOS cascode transistor during normal operation such that the pullup resistance matches the pulldown resistance, and turns off the PMOS cascode transistor to shut off the pullup path during a 5V short condition. N-wells of the PMOS pullup and cascode transistors are connected to the 3.3V supply via a resistor.