CMOS Image Sensor Isolation Region Design for Dark Current Reduction
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Solution Overview
Problem
Current CMOS image sensors face challenges in optimizing the separation between light-receiving and logic regions to minimize interference and enhance electric characteristics, such as reducing dark current and improving light reflection and refractive index management.
Innovation Solution
The CMOS image sensor design incorporates a semiconductor substrate with distinct conductivity types for light-receiving and logic regions, utilizing a first device isolation layer with a lower refractive index than the substrate to reflect incident light and prevent charge leakage, and a second device isolation layer with a shallower depth to define the logic region, along with NMOS and PMOS transistors and micro-lenses for efficient light guidance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single device isolation layer is used to separate light-receiving and logic regions, then manufacturing process is simplified, but electric characteristics deteriorate due to insufficient separation and increased dark current
Solution Approach 1:
The device isolation structure is divided into two distinct layers: a first device isolation layer extending deeper into the semiconductor substrate to provide electrical separation and reduce dark current, and a second device isolation layer positioned shallower to define the logic region. This segmentation allows each layer to perform its specific function optimally, resolving the contradiction between manufacturing simplicity and electric characteristic performance.
2Reliability
If the device isolation layer extends deeply into the substrate to reduce dark current, then electric characteristics improve, but manufacturing complexity increases due to deeper etching requirements
Solution Approach 1:
The isolation function is segmented into two layers with different depths. The first device isolation layer extends deeper to reduce dark current by providing effective electrical separation, while the second device isolation layer is positioned shallower to define the logic region. This segmentation allows the deep isolation function to be achieved without requiring a single uniformly deep layer, thereby managing manufacturing complexity through functional division.
Solution Approach 2:
Different regions of the device isolation structure have different depths tailored to their specific functions. The first device isolation layer has greater depth in regions where dark current reduction is critical, while the second device isolation layer has shallower depth where logic region definition is the primary concern. This local differentiation of quality (depth) optimizes performance while managing manufacturing complexity.
3Measurement precision
If the photoelectric conversion layer extends deeply to improve light reception, then light sensitivity improves, but interference with logic region increases due to closer proximity
Solution Approach 1:
The device isolation structure is segmented into two layers that collectively provide sufficient separation between the photoelectric conversion layer and the logic region. The first device isolation layer extends deeper to provide electrical separation and reduce dark current, while the second device isolation layer positions the logic region boundary. This segmentation allows the photoelectric conversion layer to extend deeply for improved light reception sensitivity without causing excessive interference with the logic region, as the dual-layer isolation provides comprehensive separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the separation between light-receiving and logic regions, reducing dark current, improving light reflection, and maintaining the electric characteristics of NMOS and PMOS transistors, leading to improved image sensor performance and resolution.
Implementation Method 1
a first device isolation layer in the semiconductor substrate to define the light-receiving region of each of the pixel regions. The first device isolation layer may be adjacent a sidewall of the photoelectric conversion layer... The first device isolation layer may include an insulating layer including a first refractive index that is smaller than a second refractive index of the semiconductor substrate
Implementation Method 2
a photoelectric conversion layer of a second conductivity type in the light-receiving region of the semiconductor substrate
Data Source
AI summary
CMOS image sensors are provided. A CMOS image sensor may include a semiconductor substrate including a light-receiving region and a logic region adjacent the light-receiving region. The CMOS image sensor may include a photoelectric conversion region in the light-receiving region. Moreover, the CMOS image sensor may include an isolation region including an interface with a sidewall of the photoelectric conversion region. The isolation region may include a first refractive index that is smaller than a second refractive index of the semiconductor substrate, and the isolation region may be between the logic region and the sidewall of the photoelectric conversion region.