CMOS Library Architecture for Leakage Power Reduction
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Solution Overview
Problem
The increasing impact of process variations and transistor leakage currents in integrated circuits due to scaling, leading to high power consumption and heat generation, particularly in the OFF-state of MOSFETs, necessitates a reduction in leakage current while maintaining efficient fabrication and feature size reduction.
Innovation Solution
The use of CMOS cell libraries with MOSFETs of varying channel lengths, including pairs of isolation MOSFETs evenly spaced at equal pitch, to minimize leakage current and achieve smaller feature sizes, leveraging long-channel transistors and gate-isolation techniques for reduced leakage and increased regularity in logic gate patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If transistor physical size and operating voltage are scaled down to increase integration density, then device miniaturization is achieved, but process variations and leakage currents increase dramatically
Solution Approach 1:
The patent applies local quality by creating different threshold voltage regions within the same transistor array. Specific transistors are transformed into high-Vt devices through well-tap modifications, while others maintain low-Vt characteristics. This localized differentiation allows critical transistors to have reduced leakage without compromising the speed of timing-critical paths, thus resolving the contradiction between miniaturization and performance robustness.
2Loss of energy
If high Vt transistors are used to reduce subthreshold leakage current, then leakage power is reduced, but logic gate delay increases due to reduced current driving capability
Solution Approach 1:
The patent implements local quality by selectively transforming only certain transistors into high-Vt devices based on their functional role. Non-critical transistors receive well-tap modifications for high-Vt operation to reduce leakage, while timing-critical transistors maintain low-Vt for speed. This selective approach resolves the contradiction between leakage reduction and speed maintenance.
Solution Approach 2:
The patent segments the transistor population into different categories based on their leakage-criticality. By dividing transistors into those requiring leakage reduction and those requiring speed optimization, the system can apply different Vt characteristics to different segments, thus resolving the contradiction between energy loss and speed.
3Loss of energy
If additional implants or doping modifications are used to control punchthrough and reduce leakage, then leakage current is reduced, but fabrication cost increases
Solution Approach 1:
The patent changes the electrical parameters of existing transistors by modifying well-tap connections rather than adding physical implants or doping layers. This parameter transformation approach achieves leakage reduction through electrical reconfiguration instead of additional fabrication steps, thus resolving the contradiction between leakage current reduction and fabrication cost.
Data Source
AI summary
Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes.