CMOS Differential Logic With Voltage Boosting for Low-Voltage Speed
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Solution Overview
Problem
Conventional CMOS differential logic circuits experience significant speed degradation and increased energy consumption when operating at low source voltages, limiting their efficiency and performance in portable devices.
Innovation Solution
A CMOS differential logic circuit using a voltage boosting technique that employs capacitive coupling to increase the gate-source voltage of transistors, allowing for high-speed operation at low source voltages while reducing energy consumption by utilizing only one bootstrapped capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If voltage scaling is applied to reduce energy consumption, then energy efficiency is improved, but operating speed is severely degraded
Solution Approach 1:
The circuit performs preliminary action by precharging the differential logic unit to source voltage before the actual switching operation. This precharging ensures that the logic unit is ready to switch quickly when the clock signal transitions, compensating for the slow switching caused by low source voltage and maintaining high operating speed while operating at reduced voltage for energy efficiency.
Solution Approach 2:
The invention changes the voltage parameter dynamically by using a clock signal to control the switching between precharged state and output state. The differential logic unit operates at low source voltage for energy efficiency, but the output can reach full source voltage level through the switching mechanism, thus resolving the contradiction between low-voltage operation and high-speed output.
2Use of energy by moving object
If source voltage is scaled down toward threshold voltage for maximum energy efficiency, then energy consumption is minimized, but switching current is severely reduced causing speed degradation
Solution Approach 1:
The precharging phase accumulates charge in the differential logic unit before the switching event, ensuring that sufficient charge is available for rapid switching. This preliminary charge accumulation allows the circuit to maintain high switching current during the brief switching interval even though the average current at low voltage is reduced, thus achieving both energy efficiency and adequate switching current.
3Speed
If conventional DCVS circuit is used for high-speed operation, then operating speed is maintained, but output current is proportional to source voltage causing energy inefficiency at low voltages
Solution Approach 1:
The circuit uses periodic clock signal transitions to alternate between precharging phase and output phase. During the precharging phase, the logic unit is charged to source voltage; during the output phase, the switched output delivers the signal. This periodic operation allows the circuit to achieve high-speed performance during the output phase while consuming minimal energy during the precharging phase, resolving the contradiction between speed and energy efficiency.
4Speed
If bootstrapped dynamic logic is used to improve switching speed at low source voltage, then operating speed is improved, but circuit complexity increases due to additional capacitors and transistors
Solution Approach 1:
The invention merges the precharging function and the logic operation into a single differential logic unit. The same unit that performs the logic function also serves as the precharged element, eliminating the need for separate precharging circuits and capacitors. This integration reduces circuit complexity while maintaining the voltage boosting effect that improves switching speed at low source voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly improves operating speed and energy efficiency by reducing propagation delay and energy consumption, achieving a 89% reduction in delay time and maintaining energy efficiency comparable to existing static CMOS logic at low source voltages.
Implementation Method 1
capacitive coupling of a MOS transistor for transferring a signal from an input terminal to an output terminal
Data Source
AI summary
The present invention discloses a CMOS differential logic circuit. The CMOS differential logic circuit includes a precharge differential logic unit, which is precharged to a source voltage in response to a clock signal and is configured to output voltage having an increased load-driving ability using a boosting voltage; a voltage-boosting unit, which is pulled down by a ground voltage in response to the clock signal and is configured to boost the pulled-down voltage using capacitive coupling and output the boosting voltage; and a switching unit, which is configured to couple the precharge differential logic unit and the voltage-boosting unit in response to the clock signal. The propagation delay of a signal from the input terminal to the output terminal of a circuit in a low-source-voltage environment can be reduced, and the operating speed of the circuit and energy efficiency of the operation thereof can be improved.