CMOS Non-Volatile Memory Cell With Three-Transistor Read-Program-Erase
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Solution Overview
Problem
Existing non-volatile memory cells require complex semiconductor processes and multiple transistors to perform basic operations like erase, program, and read modes, making them cumbersome to fabricate and layout.
Innovation Solution
A simplified non-volatile memory cell design using a tunneling part, a coupling transistor, a read transistor, and a select transistor, all fabricated through a CMOS process, which reduces the number of transistors and devices needed to perform these operations, with a charge storage node that forms electron tunneling paths for erase and program modes and a read path for read mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If five transistors and devices are used to implement non-volatile memory cell operations, then the basic operations (erase, program, read modes) can be performed, but the device complexity and manufacturing complexity increase significantly
Solution Approach 1:
The patent combines multiple functions into a single memory cell structure that uses only three transistors. The first transistor serves as both a coupling transistor and part of the tunneling structure, the second transistor functions as both a read transistor and controls electron tunneling, and the third transistor acts as both a select transistor and part of the read path. This merging of functions reduces the total transistor count from five to three while maintaining all necessary operations (erase, program, read modes).
Solution Approach 2:
Each transistor in the simplified design performs multiple functions. For example, the second transistor not only acts as a read transistor but also controls the electron tunneling injection path during program mode and the electron tunneling ejection path during erase mode. This multi-functionality allows the reduced transistor count to still achieve complete operational capability.
2Adaptability or versatility
If five transistors and devices are arranged on multiple wells, then the memory cell operations are achieved, but the manufacturing process becomes complicated
Solution Approach 1:
The patent merges the memory cell structure to require only three transistors that can be implemented on a single P-well or N-well, eliminating the need for multiple independent wells. This consolidation simplifies the semiconductor fabrication process by reducing the number of well formation steps, implantation steps, and isolation structures required, while still achieving all necessary memory operations through the multi-functional transistor design.
3Reliability
If more transistors and devices are used, then the memory cell can perform all operations reliably, but the layout area increases
Solution Approach 1:
By merging multiple functions into three transistors, the patent significantly reduces the layout area compared to the five-transistor design. The compact structure places all necessary components (three transistors, tunneling part, conductive regions) in a smaller footprint, while the multi-functional design ensures that all operations (erase, program, read) remain reliable through proper voltage control and electron tunneling mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design allows for efficient operation in erase, program, and read modes with fewer transistors and devices, simplifying the manufacturing process and reducing layout area, while maintaining functionality.
Implementation Method 1
When the non-volatile memory cell is operated in the erase mode, the electron tunneling effect occurs in the erase transistor 120. Electrons are tunneling ejected from a floating gate FG1 of the read transistor 110; when the non-volatile memory cell is operated in the program mode, the electrons are tunneling injected to the floating gate FG1 of the read transistor 110
Data Source
AI summary
A non-volatile memory cell includes a tunneling part; a coupling transistor, including a coupling gate part, a first conductive region and a second conductive region, wherein the coupling gate part is coupled to the tunneling part and disposed in the first conductive region; a read transistor with a read gate part coupled to the tunneling part for forming an electron tunneling ejection path in an erase mode, and forming an electron tunneling injection path in a program mode; and a select transistor, connected in series with the read transistor, for forming a read path with the read transistor in a read mode.