CMOS Image Sensor and MIM Capacitor Integration via Shared Metal Layers
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Solution Overview
Problem
The challenge in the semiconductor industry is to integrate various integrated circuit devices, such as CMOS image sensors and MIM capacitors, on a single semiconductor substrate efficiently, while existing methods are complex and costly.
Innovation Solution
The integration of a CMOS image sensor and a MIM capacitor is achieved by forming a polysilicon plug and transistor gate in a dielectric layer, with a stacked metal layer connecting them, and using the same metal layer for both devices, thereby simplifying processes and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate fabrication processes are used for CMOS image sensors and MIM capacitors, then each device can be optimized independently, but the manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent combines the fabrication processes for CMOS image sensors and MIM capacitors into a single integrated process flow. The metal layers, dielectric layers, and processing steps are merged so that both devices are manufactured simultaneously on the same substrate, eliminating the need for separate fabrication lines and reducing overall manufacturing complexity.
Solution Approach 2:
The patent creates a universal fabrication process that serves multiple functions: forming photodiodes, transistors, interconnects, and MIM capacitors all through the same sequence of deposition and patterning steps. This multi-functional approach allows a single process to optimize multiple device types without requiring device-specific process variations.
2Manufacturing precision
If multiple separate metal layers are deposited for different devices, then each device structure can be precisely controlled, but the number of processing steps and production cost increase
Solution Approach 1:
The patent merges the metal layer deposition for CMOS image sensor interconnects with the metal layer deposition for MIM capacitor electrodes. The same metal layers (first metal layer, second metal layer, third metal layer) are used for both purposes, eliminating redundant deposition steps while maintaining precise structural control through selective patterning.
Solution Approach 2:
The metal layers are designed to serve dual functions: forming electrical interconnects for the image sensor circuitry and forming the electrode structures for MIM capacitors. This universal use of metal layers increases productivity by reducing the total number of deposition cycles required.
3Manufacturing precision
If different processing sequences are used for image sensors and capacitors, then each device can be fabricated with optimal parameters, but the overall fabrication time and cost increase
Solution Approach 1:
The patent performs preliminary actions by forming all metal layers and dielectric layers in a unified sequence before final device-specific patterning. The common structural elements (metal interconnects, capacitor electrodes, insulating layers) are prepared in advance through shared processing steps, reducing the total fabrication time while maintaining optimal parameters for each device type in the final patterning stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the simultaneous formation of CMOS image sensors and MIM capacitors with shared metal layers and processes, reducing complexity and processing costs, and achieving a more stable and efficient integrated circuit device.
Implementation Method 1
the lower metal layer includes a first metal silicide part contacting to the polysilicon plug
Data Source
AI summary
An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.