CMOS Digital-to-Phase Converter With Slew-Controlled Clock Mixing
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Solution Overview
Problem
Existing digital-to-phase converters for high-speed serial communication links face challenges such as complexity, high manufacturing costs, and inaccuracy due to the use of current-mode logic (CML) and complementary-metal oxide semiconductor (CMOS) logic, which do not scale well with shrinking fabrication technology and have nonlinear relationships between phase control and sampling clock signals.
Innovation Solution
A digital-to-phase converter circuit that includes pre-driver modules to produce complementary buffered clock signals with controlled slew rates and mixer modules to form a weighted combination of these signals based on a phase control input, allowing for digitally controlled phase outputs, thereby addressing the nonlinearities and scalability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current-mode logic (CML) is used in digital-to-phase converters, then the circuit can operate at high speeds, but the device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent replaces CML circuits with CMOS logic circuits in the digital-to-phase converter. Specifically, the phase interpolator is implemented using CMOS logic gates (AND, OR, NOT gates) instead of CML circuits, eliminating the need for complex CML-to-CMOS and CMOS-to-CML converter interfaces while maintaining compatibility with standard CMOS fabrication processes.
2Speed
If current-mode logic (CML) is used in digital-to-phase converters, then the circuit can operate at high speeds, but the manufacturing cost increases
Solution Approach 1:
The patent replaces CML circuits with CMOS logic circuits in the digital-to-phase converter. Specifically, the phase interpolator is implemented using CMOS logic gates (AND, OR, NOT gates) instead of CML circuits, eliminating the need for complex CML-to-CMOS and CMOS-to-CML converter interfaces while maintaining compatibility with standard CMOS fabrication processes.
3Adaptability or versatility
If prior digital-to-phase converter designs are used, then the circuit can be implemented with existing technology, but the phase control accuracy deteriorates due to nonlinear relationships
Solution Approach 1:
The patent applies preliminary calibration to compensate for nonlinearities in the phase interpolator. During the calibration process, the actual phase output of the interpolator is measured at various control code settings, and calibration values are stored in lookup tables. During normal operation, these calibration values are used to correct the phase control signal, ensuring accurate phase control despite the inherent nonlinearities of the CMOS-based interpolator circuitry.
Data Source
AI summary
Systems and methods for converting digital signals into clock phases are disclosed. An example digital-to-phase converter circuit receives a complementary in-phase and quadrature clock signals and produces four clock outputs at a phase controlled by a digital phase control input. The digital-to-phase converter uses first and second pre-driver modules to buffer the -phase and quadrature clock signals and produce corresponding buffered clock signals having controlled slew rates. Mixer modules produce the clock outputs by forming weighted combinations of the buffered clock signals. The weighting is determined based on the phase control input. The controlled slew rates of the buffered clock signals allow digital mixer module to provide accurate phase control. The digital-to-phase converter may also include an output buffer that compensates for nonlinearities in the relationship between the phases of the clock outputs and the phase control input.