CMOS Phase Interpolator Using Current-Controlled Capacitor Charging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing phase interpolators for digital and mixed-signal systems face challenges in achieving high phase resolution and linearity, especially when operating on CMOS rail-to-rail clock signals, due to limitations in the number of inverters that can be switched and the resulting coarse quantization.
Innovation Solution
A phase interpolator circuit that directly operates on CMOS rail-to-rail clock signals by using a voltage comparator and switchable current sources to charge an output node, allowing for variable current magnitudes to adjust the phase shift of the output clock signal, thereby improving phase resolution and linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple CMOS phase interpolator is implemented by dotting together the outputs of multiple CMOS inverters driven by different clock phases, then the circuit complexity is reduced and power efficiency is improved, but the interpolation linearity deteriorates and phase resolution becomes coarse
Solution Approach 1:
The patent changes the operating parameters by using variable current magnitudes from a current-mode DAC to control the charging rate of the output capacitor, enabling continuous phase adjustment with high resolution. This replaces the discrete inverter-switching approach with a continuous current-controlled charging mechanism, achieving both high phase resolution and improved linearity while maintaining CMOS compatibility.
Solution Approach 2:
The patent substitutes the mechanical switching of multiple inverters with an electrical current-controlled charging system. Instead of physically switching between discrete inverter outputs, the system uses a voltage comparator and variable current sources to electronically adjust the phase, eliminating the need for multiple physical inverter stages and achieving finer phase control.
2Use of energy by moving object
If the number of inverters that can be switched in is limited due to area and power considerations, then the area and power consumption are reduced, but the quantization of the resulting interpolation becomes relatively coarse
Solution Approach 1:
The patent uses a current-mode DAC to provide variable current magnitudes that directly control the charging rate of the output capacitor. By changing the current parameter continuously rather than switching between fixed numbers of inverters, the system achieves high phase resolution with minimal area and power consumption, as only a single capacitor and current source are needed instead of multiple parallel inverters.
3Measurement precision
If CML phase interpolators are used to achieve high phase resolution, then the phase resolution is improved, but the circuit complexity increases due to CMOS-to-CML converters and pre-conditioning slew-rate-limiters
Solution Approach 1:
The patent extracts and eliminates the unnecessary conversion stages by designing a phase interpolator that operates natively in CMOS logic levels. By removing the CMOS-to-CML converters and slew-rate-limiters from the signal path, the system achieves high phase resolution while significantly reducing circuit complexity and maintaining compatibility with standard CMOS clock distribution networks.
Solution Approach 2:
The patent substitutes the CML-based interpolation mechanism with a CMOS-compatible voltage comparator and current-source system. This replacement eliminates the need for level conversion circuits and pre-conditioning stages, achieving the same high phase resolution function using simpler CMOS circuitry that integrates more easily with modern digital systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-resolution phase interpolation with improved linearity, allowing for sharper transitions and reduced circuit complexity, making it more attractive for high-performance digital and mixed-signal systems.
Implementation Method 1
by switchably connecting a first current source to an output node to apply a first current that charges a capacitance of the output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator circuit
Implementation Method 2
detecting an arrival of an edge of the second input clock signal and in response to the detecting, by switchably connecting a second current source to the output node to apply a second current that charges the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator circuit
Data Source
AI summary
A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.