Equalisers TRIZ Cases

An amplifying adder boosts PAM-4 eye size within a defined input range, enabling reliable sampling with lower comparator power.

A dual-receiver PAM eye diagram uses complementary sampling data to tune equalizer settings and offset insertion loss, noise, and ISI.

An active inductor with op-amp feedback lets a CTLE extend bandwidth and hold Nyquist peaking while cutting area and power.

Receiver feedback on unequal PAM voltage steps lets the transmitter retune drive strength and improve high-speed data recovery.

Receiver feedback detects unequal PAM voltage spacing and tunes transmitter drive strength to reduce nonlinear distortion in high-speed links.

Receiver feedback detects unequal PAM voltage spacing and tunes transmitter drive strength to reduce nonlinear distortion and improve data recovery.

A magnification parameter adjusts multiple EQ point gains at once, simplifying digital mixer equalizer tuning without losing band-level control.

Time borrowing across multi-phase sampled bits relaxes feedback-path delay, helping partial response equalizers run at higher data rates with less ISI.

Dual-path equalization and offset cancellation preserve comparator accuracy without slowing high-speed receiving circuit processing.

Amplitude offsets add overlay data to legacy COFDM signals while receiver equalization preserves backward compatibility and signal recovery.

Overlapping clock signals and staged latches cut symbol identification time to 20-25 ps, enabling accurate high-frequency data transfer.

Variable current sources charge an output node capacitor to improve CMOS clock phase resolution and linearity without CML conversion.

Variable charging currents and comparator thresholding enable finer CMOS clock phase steps with better linearity and less circuit complexity.

A dual-error adaptive equalizer corrects polarization crosstalk and mode dispersion in probabilistic shaping systems to lower bit error rate.

A wireless receiver switches between time- and frequency-domain equalization based on channel conditions to cut power use without losing signaling efficiency.

SNR-driven coefficient update control cuts equalization, carrier recovery, and IQ imbalance power with minimal accuracy loss.

Applies AI-based correction factors across demodulation elements to cancel non-linear noise and I/Q imbalance in satellite links.

Opposite offset voltages and targeted amplification prevent upper and lower eye clipping, improving receiver data restoration while limiting area.

Coherent averaging and self-timed packet alignment improve ultrawideband channel models despite path loss, Doppler, and clock drift.

This case shows how feed ports and cross-channel equalization reduce self-interference and clutter for proximity detection under MPE limits.

This case assigns non-linear equalization and retiming to the host ASIC, simplifying optical modules and reducing power and cost.

This case partitions equalization between optical module and host ASIC to reduce redundant processing while preserving signal quality.

An adaptive equalizer adjusts settings using signal modulation results during handshake operations in memory storage devices.

An integrated equalization circuit merges feed-forward and decision feedback stages with a variable gain amplifier to reduce noise in serial links.

Coarse and fine tuning modules adjust equalization strength in two stages, resolving performance degradation at 5.4 GHz caused by fixed equalization limits.

Multiplexing fixed sequence divisions at block ends suppresses out-of-band power from phase discontinuity while maintaining transmission efficiency.

Continuous time linear equalization compensates for impedance mismatches and noise in high-speed RAM data signals by adjusting gain peaks.

A sampling frequency offset estimation apparatus calculates individual pilot subcarrier phase shifts to determine precise time offsets.

A decision feedback equalizer with programmable taps and a weight generator adjusts tap weights to improve signal quality.

A PAM-4 DFE architecture applies weighted raw sampler outputs directly to reduce feedback latency without decoding.

Segmenting filters by mode reduces inter-frame interference while maintaining compatibility with existing communication standards.

Iterative quasi-linear receiver estimates filter weights to cancel co-channel interference, boosting system throughput without adding antennas.

A noise guessing decoder iteratively hypothesizes corrupted sequences to invert signal distortion and recover valid codewords.

A processor optimizes high-speed data communication links by adjusting equalization settings based on a calculated link score.

A receiver adaptation system adjusts frequency response parameters using stochastic hill climbing and genetic mutation to optimize signal quality.

Merging feed-forward equalization with crosstalk cancellation reduces system complexity while maintaining signal quality.

A multiplexer-less decision feedback equalizer processes intersymbol interference cancellation signals directly at reduced data rates.

Dynamic unique word configuration minimizes signaling overhead while maintaining signal processing precision across varying wireless channel conditions.

A transmitter driver circuit adjusts gate voltages of series-connected PMOS and NMOS transistors to perform signal driving and equalizing operations.

A hybrid equalizer loop combines frequency and time domain processing to compensate chromatic dispersion in optical signals.

Mapping intervals reciprocal to spacing ratios reduce cross-correlation between ZC sequences, enhancing channel estimation accuracy.

Averages transfer functions estimated at multiple frequency offsets to maintain compensation accuracy despite laser fluctuations.

Spreads data symbols across two-dimensional resource domains to maintain orthogonality despite channel degradation in 5G systems.

A transmitter driver uses a high frequency booster to inject current into the output path, enhancing voltage swing for high speed data transmission.

Complementary device inverters replace traditional amplifier stages in a CTLE circuit, enabling high-speed signal equalization at reduced voltage levels.

Iterative updater refines frequency domain values through signal decision feedback to enhance receiver system reliability.

Parallel filterbanks process time-domain derivatives to equalize FBMC signals, reducing distortion in high frequency selectivity channels.

A level equalization technique adjusts signal levels using binning and polynomial transformations to correct distortions in optical receivers.

Unified generator shifts basic scrambling codes through 4096 chips to produce preambles, eliminating separate digital signal processor transmission.

A decision feedback equalizer uses fractional tap unrolling to track preceding symbol decisions and adjust thresholds for accurate signal recovery.

A multichannel passive intermodulation digital cancellation circuit generates interference signals to compensate for channel inconsistencies.

An adaptive equalizer compares signal amplitude and boost measurements to calibrate PAM4 signals via reference amplification modification.