Multi-Phase Partial Response Equalizer With Time-Borrowing Feedback
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Solution Overview
Problem
Conventional partial response equalizers face challenges in high data rate applications due to the limitations imposed by the longest feedback path delay, which restricts their ability to maintain signal quality as clock rates increase, leading to inter-symbol interference (ISI) and degradation of signal distinctions.
Innovation Solution
The implementation of a multi-data rate partial response equalizer that employs a time borrowing technique, allowing for increased time for signal propagation between sampled bits without altering the clock signal periods, thereby reducing timing constraints and enabling operation at higher data rates by adjusting the clock-to-Q output delay, select-to-output delay, and setup delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional partial response equalizer is used, then signal quality can be maintained at lower data rates, but the longest feedback path delay restricts operation at higher clock rates
Solution Approach 1:
The feedback path is segmented into multiple parallel paths with different delay elements (TD1, TD2, TD3) and corresponding multiplexers (MUX1, MUX2, MUX3). Each path processes a different portion of the feedback signal, allowing the overall system to handle higher clock rates by distributing the timing requirements across multiple shorter paths rather than one long sequential path.
Solution Approach 2:
The design transitions from a single-dimensional sequential feedback path to a multi-dimensional parallel structure. By introducing multiple feedback paths operating in parallel with different delay characteristics, the system adds a dimensional aspect to the feedback mechanism, enabling higher data rates while maintaining signal quality through selective combination of path outputs.
2Productivity
If parallel sampling paths are used, then two bits can be sampled per clock period, but the longest feedback path delay still imposes a lower limit on unit interval
Solution Approach 1:
The feedback path is segmented into multiple parallel paths with different delay elements (TD1, TD2, TD3) and corresponding multiplexers (MUX1, MUX2, MUX3). Each path processes a different portion of the feedback signal, allowing the overall system to handle higher clock rates by distributing the timing requirements across multiple shorter paths rather than one long sequential path.
Solution Approach 2:
The system dynamically selects which feedback path to use based on the current data conditions. The multiplexers (MUX1, MUX2, MUX3) enable dynamic switching between different feedback paths with varying delay characteristics, allowing the equalizer to adapt to different signaling conditions and optimize performance for higher data rates.
3Productivity
If clock rate is increased to achieve higher data rates, then productivity improves, but inter-symbol interference increases and signal distinctions are lost
Solution Approach 1:
The patent implements a feedback mechanism where previously sampled bits are fed back through multiple paths with different delays and combined with current samples. This feedback equalization compensates for the inter-symbol interference caused by high-speed transmission by reconstructing and subtracting the interference components from the received signal.
Solution Approach 2:
The equalizer combines multiple feedback paths with different delay characteristics to create a composite equalization response. By synthesizing multiple partial responses with different delay profiles, the system creates a composite effect that effectively mitigates ISI across a broader frequency range, enabling higher data rate operation.
Data Source
AI summary
A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.