High-Speed Data Link Training via System-Level Optimization

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Solution Overview

Problem

Traditional methods for training high-speed data communication interfaces often fail to optimize link performance across all lanes, leading to suboptimal results due to inadequate consideration of cross-talk effects and increased power consumption, as they focus on per-lane optimization rather than system-level optimization.

Innovation Solution

A system-level optimization approach that determines a link score based on lane quality functions for each lane, identifies the lane with the greatest magnitude quality value, and iteratively adjusts the equalization settings to achieve a satisfactory link score, ensuring optimal performance and reduced power consumption across the entire high-speed data communication link.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If per-lane optimization is used for training high-speed data communication interfaces, then individual lane performance is improved, but system-level link performance deteriorates due to inadequate consideration of cross-talk effects

Engineering Contradiction:
Improvelane performanceVSAvoidlink performance
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent merges individual lane training into a unified system-level training process. Instead of optimizing each lane independently, the method trains all lanes simultaneously while considering their interactions, particularly cross-talk effects. This is achieved by evaluating link quality based on combined lane quality functions and iteratively adjusting equalization settings across the entire link to maximize overall link quality, thereby resolving the contradiction between individual lane performance and system-level reliability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the optimization parameter from individual lane equalization settings to system-level link quality. By defining a link quality metric that incorporates contributions from all lanes and their interactions, the method shifts the optimization focus from isolated lane parameters to comprehensive link performance parameters. This enables the training process to account for cross-talk and other system-level effects that per-lane optimization cannot capture.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If per-lane training is performed for all lanes, then comprehensive coverage is achieved, but power consumption increases due to redundant adjustments

Engineering Contradiction:
Improvetraining completenessVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies local quality by identifying and focusing training efforts on specific lanes that contribute most to link quality improvement. Rather than uniformly adjusting all lanes, the method evaluates the impact of each lane on overall link performance and prioritizes adjustments to lanes with greater impact. This selective approach maintains training completeness for reliable link optimization while reducing power consumption by avoiding redundant adjustments to lanes with minimal impact.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements partial action by performing training adjustments only on a subset of lanes that are most critical to link quality. The iterative process identifies lanes whose equalization settings have the greatest influence on link quality and focuses computational and power resources on optimizing those specific lanes. This partial approach achieves sufficient training completeness for reliable operation while significantly reducing the power consumption associated with comprehensive all-lane training.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If equalization settings are adjusted for all lanes during training, then overall link quality may improve, but training complexity and time increase

Engineering Contradiction:
Improvelink qualityVSAvoidtraining complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the training process into iterative phases, where in each iteration only a subset of lanes is selected for adjustment based on their contribution to link quality. Rather than simultaneously optimizing all lanes (which would create combinatorial complexity), the method divides the training task into manageable segments, focusing on one or a few key lanes per iteration. This segmentation dramatically reduces training complexity while still achieving reliable link quality through cumulative improvements across multiple iterations.

Inventive Principle:
Principle #1Segmentation

4Ease of manufacture

If traditional per-lane training methods are used, then implementation is simpler, but cross-talk effects between lanes are not adequately considered

Engineering Contradiction:
Improveimplementation simplicityVSAvoidcross-talk consideration
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent implements feedback by using measured link quality as a guide for iterative equalization adjustments. The system measures the actual link quality after initial training, compares it to target performance levels, and uses this feedback to identify which lanes require further optimization. This feedback-driven approach systematically addresses cross-talk effects by continuously evaluating their impact on link quality and adjusting settings accordingly, achieving reliable cross-talk consideration without excessive implementation complexity.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11757685B1System level optimization for training a high-speed data communication interface
Publication Date: 2023.09.12 DELL PROD LP
  • US11757685B1 patent drawing
  • US11757685B1 patent drawing
  • US11757685B1 patent drawing

AI summary

An information handling system includes a high-speed data communication link and a processor. The link includes lanes that each includes a transmitter with an equalization setting and a receiver. The processor initiates a training of the high-speed data communication interface to determine a setting value for the equalization setting for each lane, determines a lane quality value for each lane based upon the associated setting value, determines a link score based on the lane quality values, and determines that the lane quality score is outside a threshold range. In response to determining that the lane quality score is outside the threshold range, the processor selects a lane that has a lane quality value that has a greater magnitude than the lane quality values of all other lanes, increases the equalization setting of the first lane, and initiates a retraining of the other lanes.