Mux-less Decision Feedback Equalizer for High-Speed Data
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Solution Overview
Problem
Conventional decision feedback equalizers (DFEs) at high-data rates require multiplexing back to full-rate for ISI cancellation, which increases power consumption and feedback delay, detrimental at high-data rates.
Innovation Solution
A multiplexer-less (mux-less) DFE design that combines K intersymbol interference (ISI) cancellation signals with an input signal using summing circuits and RZ latches, eliminating the need for multiplexing, thereby reducing power requirements and feedback delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is multiplexed back to full-rate for ISI cancellation in conventional DFEs, then ISI cancellation is achieved, but power consumption increases and feedback delay increases
Solution Approach 1:
The patent extracts and removes the multiplexer component from the conventional DFE architecture. By eliminating the multiplexer that converts 1/K-rate data back to full-rate, the system achieves ISI cancellation directly at the reduced data rate, thereby removing the source of excessive power consumption associated with multiplexing operations while maintaining the essential feedback equalization function.
Solution Approach 2:
The patent segments the feedback path into K parallel branches operating at 1/K-rate, with each branch having its own summing circuit and feedback loop. This segmentation allows independent processing of feedback signals at the reduced data rate without requiring consolidation to full-rate, enabling power-efficient operation while maintaining effective ISI cancellation across all data streams.
2Reliability
If data is multiplexed back to full-rate for ISI cancellation in conventional DFEs, then ISI cancellation is achieved, but feedback delay increases
Solution Approach 1:
The patent extracts and removes the multiplexer from the feedback path, eliminating the time-consuming multiplexing operation that converts 1/K-rate data back to full-rate. This removal directly reduces feedback delay by allowing the feedback loop to operate continuously at the lower 1/K-rate without periodic rate conversion, thereby improving the timeliness of ISI cancellation.
Solution Approach 2:
The patent segments the feedback system into K independent parallel paths that operate simultaneously at 1/K-rate. Each segmented path processes feedback signals independently without requiring consolidation to full-rate, thereby eliminating the time penalty associated with multiplexing and reducing overall feedback delay while maintaining comprehensive ISI cancellation coverage.
3Productivity
If multiplexer is used in DFE for ISI cancellation, then full-rate data processing is achieved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the multiplexer component from the DFE architecture. By removing this complex device, the system achieves data processing at 1/K-rate through simpler parallel circuitry, thereby reducing device complexity while maintaining effective ISI cancellation functionality through the segmented feedback approach.
Solution Approach 2:
The patent replaces the complex multiplexer-based full-rate processing architecture with K segmented parallel branches operating at 1/K-rate. Each branch uses simple summing circuits and feedback loops that can be implemented with basic analog or digital components, significantly reducing overall device complexity while achieving comparable or superior performance through parallel processing.
Data Source
AI summary
The present disclosure relates to a 1/K-rate decision feedback equalizer (DFE) and to a decision feedback equalization method. The DFE comprises: (i) a summing circuit configured to combine K intersymbol interference (ISI) cancellation signals with an input signal of the DFE, (ii) K branches each including a reset-to-zero (RZ) latch configured to receive an output signal of the summing circuit according to a clock signal and to produce a RZ signal, and (iii) a feedback circuit including K filters each configured to receive a respective RZ signal from a respective RZ latch and to produce a respective ISI cancellation signal. The method comprises: (i) producing an output signal for K branches based on K cancellation signals and on an input signal, (ii) producing K RZ signals based on the output signal and on a clock signal, and (iii) producing the K ISI cancellation signals based on the K RZ signals.