Receiving Circuit Equalization with Offset-Canceling Dual Paths
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Solution Overview
Problem
High-speed equalization processing in receiving circuits is hindered by the connection of an offset adjusting section, which decreases the operation speed of the equalization section.
Innovation Solution
A receiving circuit configuration that includes a first adder for adding a first offset cancellation value to the input signal, a second adder for adding a first equalization value, comparators for binary decision-making, and an offset cancellation circuit that controls these values based on the preceding bit of the input signal, allowing for efficient offset cancellation without slowing down the equalization processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an offset adjusting section is connected to the equalizing section, then offset cancellation is achieved, but the operation speed of the equalizing section decreases
Solution Approach 1:
The patent divides the receiving circuit into two independent processing paths: a high-speed equalizing section that processes signals without offset adjustment, and a separate offset adjusting section that operates independently. The equalizing section performs binary decision-making at high speed using only equalization values, while the offset adjusting section separately calculates offset cancellation values based on decision results. This segmentation eliminates the speed-limiting connection between offset adjustment and equalization processing.
Solution Approach 2:
The patent introduces a selector as an intermediary component that chooses between different processing paths based on the preceding bit value. When the preceding bit is '0', the high-speed path is used; when it is '1', the offset-adjusted path is used. This intermediary allows the system to switch between speed-optimized and accuracy-optimized modes, resolving the contradiction between operation speed and offset cancellation accuracy.
2Productivity
If high-speed equalization processing is implemented, then communication speed is improved, but offset cancellation capability is compromised
Solution Approach 1:
The patent performs preliminary equalization processing on the input signal to generate an equalized signal and preliminary binary decision results. These preliminary results are then used by the offset adjusting section to calculate offset cancellation values. By performing the equalization action first (before offset adjustment), the system maintains high-speed processing while still enabling subsequent offset cancellation, thus resolving the contradiction between communication speed and offset cancellation capability.
Solution Approach 2:
The patent implements a feedback mechanism where the binary decision results from the high-speed equalizing section are fed back to the offset adjusting section. The offset adjusting section uses these decision results to calculate appropriate offset cancellation values, which are then applied to improve the accuracy of subsequent decisions. This feedback loop enables the system to maintain high communication speed while progressively improving offset cancellation capability through iterative refinement.
Data Source
AI summary
A circuit includes: a first adder configured to add a first offset cancellation value to an input signal value; a second adder configured to add a first equalization value to an output signal value from the first adder; a first comparator configured to make a binary decision on an output signal value from the second adder; a third adder configured to add a second offset cancellation value to the input signal value; a fourth adder configured to add a second equalization value to an output signal value from the third adder; a second comparator configured to make a binary decision on an output signal value from the fourth adder; a selector configured to output a determination result of the first comparator or a determination result of the second comparator in accordance with a determination result of preceding one bit of the input signal value.