CMOS Phase Interpolator Using Current-Controlled Edge Timing
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Solution Overview
Problem
Existing phase interpolators for digital and mixed-signal systems face challenges in achieving high phase resolution and linearity, especially when operating on CMOS rail-to-rail clock signals, due to limitations in the number of inverters that can be switched and the resulting coarse quantization.
Innovation Solution
A phase interpolator circuit that directly generates CMOS rail-to-rail clock signals by interpolating between two input clock phases using a controller to adjust the timing of current sources charging an output node, with a voltage comparator circuit to determine the phase shift of the output clock signal, allowing for variable current magnitudes and precise phase adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple CMOS phase interpolator is implemented by switching multiple CMOS inverters, then circuit complexity is reduced and power efficiency is improved, but phase resolution becomes coarse and interpolation linearity deteriorates
Solution Approach 1:
The interpolator core is segmented into multiple parallel current source paths, each controlled by a subset of control bits. This segmentation allows fine-grained phase control without requiring a large number of series-connected inverters, thereby achieving high phase resolution while maintaining circuit simplicity
Solution Approach 2:
The invention transitions from controlling phase through the number of series inverters (one-dimensional approach) to using parallel current paths with binary-weighted control (multi-dimensional approach). This dimensional change enables fine phase resolution through current magnitude control rather than through cascading multiple stages
2Use of energy by moving object
If CMOS rail-to-rail clock distribution is employed instead of CML clock distribution, then power efficiency is improved, but additional conversion circuits are required increasing device complexity
Solution Approach 1:
The CMOS phase interpolator is designed to be universal by directly accepting and producing CMOS rail-to-rail clock signals. The circuit performs multiple functions including phase interpolation, level conversion, and buffering within a single CMOS-optimized structure, eliminating the need for separate CMOS-to-CML and CML-to-CMOS converter circuits
Solution Approach 2:
The invention extracts and eliminates the unnecessary level conversion stages from the traditional CML-based interpolator architecture. By removing the CMOS-to-CML and CML-to-CMOS converter circuits, the design achieves power efficiency while maintaining signal compatibility throughout the signal path
3Use of energy by stationary object
If the number of inverters that can be switched is limited by area and power considerations, then device complexity and power consumption are reduced, but interpolation quantization becomes coarse
Solution Approach 1:
The invention implements dynamic current control where the magnitude of charging currents is continuously adjustable through binary-weighted control bits. This dynamic control enables fine-grained phase resolution without requiring a fixed large number of static inverter stages, allowing high precision interpolation with reduced power consumption
Solution Approach 2:
The invention changes the control parameter from discrete inverter switching counts to continuous current magnitude control. By varying the magnitude of charging currents through binary-weighted control, the system achieves fine phase resolution without being constrained by the discrete number of physical inverter stages, thereby improving interpolation precision while managing power and area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-resolution phase interpolation with improved linearity and reduced circuit complexity, achieving phase shifts equivalent to a quarter of the clock period, which is essential for precise clock signal generation in digital and mixed-signal systems.
Implementation Method 1
by switchably connecting a first current source to an output node to apply a first current that charges a capacitance of the output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator circuit
Implementation Method 2
by switchably connecting a second current source to the output node to apply a second current that charges the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator circuit
Implementation Method 3
a voltage comparator circuit to determine the phase shift of the output clock signal
Data Source
AI summary
A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.