CMOS Pixel Structure With Dual Vertical Transfer Gates for Blooming Control
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Solution Overview
Problem
Existing CMOS image sensors face challenges with blooming noise due to the planar transfer gate design, which can lead to ineffective electron readout and reduced full well capacity.
Innovation Solution
The introduction of a dual vertical transfer gate design, where a deeper first transfer gate and a shallower second transfer gate are used, enhances electron transfer and storage, thereby eliminating over-saturation and improving full well capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a planar transfer gate design is used, then the device structure is simple, but blooming noise occurs and full well capacity is reduced
Solution Approach 1:
The patent transitions from a planar (2D) transfer gate design to a vertical (3D) transfer gate structure that extends deeper into the substrate. This dimensional change allows electrons to be transferred and stored at different depths, preventing overflow to adjacent pixels and eliminating blooming noise while maintaining structural simplicity.
Solution Approach 2:
The transfer gate is divided into multiple segments at different depths: a first transfer gate at a first depth and a second transfer gate at a second depth. This segmentation allows electrons to be distributed and stored at different vertical levels, increasing full well capacity and preventing saturation-related blooming effects.
2Ease of manufacture
If a planar transfer gate design is used, then the manufacturing process is simple, but electron readout effectiveness is reduced
Solution Approach 1:
By extending the transfer gate vertically into the substrate rather than keeping it planar, the design improves electron readout effectiveness through deeper electron collection. The vertical extension allows the transfer gate to reach and collect electrons more effectively from the photodiode region while maintaining compatibility with standard CMOS fabrication processes.
3Device complexity
If a single transfer gate is used, then the device structure is simple, but over-saturation occurs reducing full well capacity
Solution Approach 1:
The single transfer gate is segmented into multiple transfer gates positioned at different depths in the substrate. The first transfer gate is positioned at a first depth and the second transfer gate at a second depth, allowing electrons to be distributed across multiple storage regions. This segmentation increases the total electron storage capacity (full well capacity) and prevents over-saturation by providing additional vertical storage space.
Solution Approach 2:
The multiple transfer gates are nested vertically within the substrate at different depth levels, with the first transfer gate positioned deeper than the second transfer gate. This nested arrangement maximizes the use of vertical substrate space for electron storage, effectively increasing full well capacity without expanding the lateral pixel area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This dual vertical transfer gate design effectively mitigates blooming noise and maintains high full well capacity, ensuring better image quality and dynamic range in CMOS image sensors.
Implementation Method 1
The pixel array responds to the light by accumulating a charge
Data Source
AI summary
A pixel structure is provided. The pixel structure includes a substrate, a photo detecting region, a first transfer gate, and a second transfer gate. The photo detecting region is in the substrate and has a first doping type. The first transfer gate includes a first portion in contact with a first side of the substrate and a second portion connected with the first portion and embedded in the substrate. An end of the second portion of the first transfer gate is adjacent to a side of the photo detecting region. The second transfer gate is adjacent to the first transfer gate. An end of the second transfer gate in the substrate is projectively over the photo detecting region. A method for manufacturing a pixel structure is also provided.