CMOS Image Sensor Pixel Structure for Higher Full Well Capacity
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Solution Overview
Problem
Current CMOS image sensing devices face challenges in maximizing the full well capacity (FWC) of photoelectric converters and channel width of pixel transistors, which affects operational characteristics and contact resistance.
Innovation Solution
The design includes a substrate with a light-receiving region and an active region, featuring elevated semiconductor patterns and fin gate structures for transistors, which enhance the contact area and channel width, thereby improving photoelectric converter efficiency and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar structures are used for semiconductor patterns and gates, then device complexity is reduced and manufacturing is easier, but full well capacity and channel width are limited
Solution Approach 1:
The patent transitions from conventional planar (2D) semiconductor patterns to three-dimensional elevated structures. The first and second semiconductor patterns are formed to protrude from the substrate surface, creating vertical dimensionality that increases the contact area between gates and semiconductor regions. This dimensional change directly enhances full well capacity and channel width without requiring additional lateral space, thereby resolving the contradiction between increased capacity and structural complexity.
Solution Approach 2:
The patent implements nested structures where gates are formed over the elevated semiconductor patterns, with insulation layers nested between them. The first gate is positioned over the first semiconductor pattern, and the second gate is positioned over the second semiconductor pattern, creating a layered nested configuration. This nesting approach maximizes the use of vertical space to increase effective channel width and contact area while maintaining a compact overall device footprint.
2Manufacturing precision
If conventional planar gates are used, then manufacturing precision requirements are lower, but contact area and channel width are insufficient
Solution Approach 1:
By elevating the semiconductor patterns vertically from the substrate, the patent creates a three-dimensional structure where gates can wrap around or contact the semiconductor patterns at multiple points. This vertical dimensionality increases the effective contact area between gates and semiconductor regions without requiring extremely precise lateral alignment, thereby maintaining reasonable manufacturing precision requirements while significantly enhancing contact area and channel width.
3Quantity of substance
If photoelectric converter size is increased to improve full well capacity, then more photo-charge can be stored, but device area increases and integration density decreases
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension through elevated semiconductor patterns. The increased height of the semiconductor patterns above the substrate creates additional volume and surface area for charge storage and transistor operation without expanding the lateral footprint of the device. This allows full well capacity to be enhanced while maintaining high integration density and compact device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the operational reliability and efficiency of image sensing devices by enhancing the full well capacity and channel width, leading to better image conversion and reduced noise.
Implementation Method 1
a photoelectric converter configured to detect the incident light to generate photo-charge carrying an image in the incident light
Data Source
AI summary
An image sensing device may include a substrate, a first gate, a photoelectric converter, a first semiconductor pattern including a floating diffusion, a second semiconductor pattern and a second gate. The substrate includes a light-receiving region and at least one active region. The first gate is arranged over the light-receiving region. The photoelectric converter is formed in the light-receiving region such that a first end of the first gate is disposed over the photoelectric converter. The first semiconductor pattern is formed over the substrate at a second end of the first gate. The first semiconductor pattern has a first height. The second semiconductor pattern is formed over the active region of the substrate. The second semiconductor pattern has a second height. The second gate is formed over the active region of the substrate to cover the second semiconductor pattern.