CMOS Active Pixel Sensor Shared Amplifier Pixel Capacitance Reduction
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Solution Overview
Problem
Shared amplifier CMOS image sensors face challenges in reducing floating diffusion capacitance, which affects the voltage signal swing due to higher capacitance from multiple floating diffusions and parasitic capacitance of interconnect layers, limiting their performance in small pixel designs.
Innovation Solution
The solution involves reducing the floating diffusion capacitance by shielding the interconnect layer with an output bus and using a deeper, more lightly doped n-type implant for the floating diffusion region, while modifying or removing the P-Well implant to decrease junction capacitance, and routing the output wire above the interconnect layer to minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple photodetectors share a common floating diffusion sense node, then pixel area is reduced and fill factor is improved, but floating diffusion capacitance increases which reduces voltage signal swing
Solution Approach 1:
The patent moves the floating diffusion sense node from the substrate plane to a higher interconnect layer (metal layer 1 or 2), utilizing the third dimension (vertical stacking) to separate the sense node from the photodetector array plane. This dimensional transition reduces parasitic capacitance while maintaining the shared amplifier architecture's area efficiency.
Solution Approach 2:
The patent introduces an intermediate structure (the elevated floating diffusion sense node connected via via holes to photodetectors) that mediates between the photodetector array and the readout circuitry. This intermediate sense node position reduces parasitic capacitance by separating the high-capacitance interconnect layers from the sense node while maintaining electrical connectivity.
2Adaptability or versatility
If floating diffusion regions are connected through interconnect layers, then shared amplifier functionality is achieved, but parasitic capacitance from interconnect layers increases sense node capacitance
Solution Approach 1:
The patent relocates the floating diffusion sense node to a higher interconnect layer, using vertical via holes to connect multiple photodetector rows to the shared sense node. This dimensional reorganization maintains the shared amplifier functionality while reducing parasitic capacitance by minimizing the horizontal interconnect path length and separating the sense node from high-capacitance metal layers.
Solution Approach 2:
The patent segments the connection path by using via holes to vertically connect photodetectors to the floating diffusion sense node, rather than using extended horizontal interconnect traces. This segmentation reduces the parasitic capacitance by breaking up the continuous high-capacitance interconnect path into discrete vertical connections.
Data Source
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Figure 3a~3b
Figure 4a~4c
AI summary
An image sensor includes a unit cell having a plurality of pixels; the unit cell comprising an amplifier input transistor that is shared by the plurality of pixels; a plurality of floating diffusions that are joined by a floating diffusion interconnect layer and are connected to the amplifier input transistor; and an interconnect layer which forms an output signal wire which shields the floating diffusion interconnect layer.