CMOS and Pressure Sensor Integration on SOI Substrate
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Solution Overview
Problem
The integration of a CMOS integrated circuit and a piezoresistive pressure transducer on a single chip is complicated by process differences between CMOS and piezoresistive pressure transducer fabrication processes, leading to high costs and complex packaging in existing methods.
Innovation Solution
A CMOS fabrication process is used to concurrently fabricate a CMOS integrated circuit and a pressure sensor on a silicon-on-insulator substrate, with a pressure sensor formed using piezoresistors in a Wheatstone bridge configuration, and a diaphragm created by removing metallization layers and using deep reactive ion etching to form cavities, simplifying integration and reducing thermal and stress impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate CMOS signal processing die and pressure sensor die are co-packaged through wirebonding, then functional integration is achieved, but packaging complexity increases, footprint increases, and cost increases
Solution Approach 1:
The patent merges the CMOS signal processing circuit and the piezoresistive pressure sensor into a single integrated chip structure. The CMOS circuit layer and sensor diaphragm layer are combined in one device, eliminating the need for separate dies and wirebonding connections. This merging approach directly resolves the packaging complexity issue while maintaining functional integration.
Solution Approach 2:
The integrated chip serves multiple functions: it processes signals through CMOS circuitry and simultaneously senses pressure through the piezoresistive diaphragm. This multi-functionality is achieved within a single device structure, avoiding the need for separate components and their associated packaging complexity.
2Adaptability or versatility
If electrochemical etch (ECE) method is used to form pressure sensor cavity, then pressure sensor is integrated on single chip, but processing complexity increases and cost increases
Solution Approach 1:
The patent replaces the electrochemical etching process with a mechanical micromachining approach. The pressure sensor cavity and diaphragm are formed through mechanical drilling and machining operations on the sensor chip, which are more straightforward and better-controlled processes compared to electrochemical etching. This substitution reduces processing complexity while achieving the same integration goal.
3Measurement precision
If piezoresistors are placed near the edge of diaphragm where stress change is high, then pressure detection sensitivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the piezoresistor placement parameters by positioning them at specific locations on the diaphragm where the stress gradient provides maximum sensitivity. The piezoresistors are arranged in a Wheatstone bridge configuration with specific geometric parameters that maximize the output signal for a given pressure input, thereby achieving high sensitivity without requiring extreme manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves fabrication efficiency, simplifies packaging, minimizes device footprint, enhances performance, and achieves cost savings by integrating the CMOS circuit and pressure sensor on a single substrate using standard CMOS processes.
Implementation Method 1
A piezoresistive pressure transducer includes a number of piezoresistors placed near the edge of a diaphragm where the stress change is high under external pressure. Accordingly, external pressure on the diaphragm stresses the diaphragm, which affects the resistance of the piezoresistors.
Implementation Method 2
a diaphragm created by removing metallization layers and using deep reactive ion etching to form cavities
Data Source
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AI summary
A device comprises a silicon-on-insulator (SOI) substrate having first and second silicon layers with an insulator layer interposed between them. A structural layer, having a first conductivity type, is formed on the first silicon layer. A well region, having a second conductivity type opposite from the first conductivity type, is formed in the structural layer, and resistors are diffused in the well region. A metallization structure is formed over the well region and the resistors. A first cavity extends through the metallization structure overlying the well region and a second cavity extends through the second silicon layer, with the second cavity stopping at one of the first silicon layer and the insulator layer. The well region interposed between the first and second cavities defines a diaphragm of a pressure sensor. An integrated circuit and the pressure sensor can be fabricated concurrently on the SOI substrate using a CMOS fabrication process.