Resistance-Free CMOS Reference Voltage Circuit With Leakage Compensation
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Solution Overview
Problem
Traditional reference voltage sources have high power consumption, large temperature coefficients, and require significant chip area due to the use of resistors and bipolar transistors, leading to poor precision and reliability in electronic systems.
Innovation Solution
A resistance-free CMOS reference voltage source designed using TSMC N12 nm CMOS technology, employing MOS tubes operating in the sub-threshold or cut-off regions to generate exponential leakage currents for high-order curvature compensation, eliminating the need for resistors and bipolar transistors, and achieving low power consumption and high precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If traditional BJT and resistor-based reference voltage source is used, then temperature compensation can be achieved, but power consumption and supply voltage increase significantly
Solution Approach 1:
The patent replaces the mechanical/electrical system based on BJT and resistors with a CMOS-based system using MOS tube leakage currents. Specifically, it uses the sub-threshold leakage currents of MOS tubes to generate temperature-dependent currents that provide temperature compensation, eliminating the need for BJT and large-value resistors, thereby significantly reducing power consumption and supply voltage requirements
Solution Approach 2:
The patent changes the operating parameters by utilizing MOS tubes in sub-threshold and cut-off regions where leakage currents exhibit strong temperature dependence. By controlling the gate-source voltages and exploiting the exponential relationship between leakage current and temperature, the system achieves temperature compensation through parameter manipulation rather than traditional component-based approaches
2Device complexity
If first-order temperature compensation is used, then circuit complexity is reduced, but temperature coefficient and precision deteriorate
Solution Approach 1:
The patent segments the temperature compensation into multiple orders by utilizing different MOS tube configurations and leakage current characteristics. The first-order compensation is achieved through basic sub-threshold MOS tube current mirrors, while higher-order compensation is achieved by incorporating cut-off region MOS tubes and their leakage currents, creating a multi-stage compensation structure that improves precision without excessive complexity
Solution Approach 2:
The patent creates a composite compensation mechanism by combining multiple MOS tube operating regions (sub-threshold and cut-off) and their respective leakage current characteristics. This composite approach integrates first-order and higher-order temperature compensation effects within a unified CMOS structure, achieving high precision temperature independence
3Measurement precision
If resistors are used for voltage-current conversion to achieve nanoampere level currents, then current precision is improved, but chip area increases significantly
Solution Approach 1:
The patent replaces the resistor-based voltage-current conversion mechanism with a MOS tube-based leakage current generation system. By utilizing the natural leakage currents of MOS tubes operating in sub-threshold and cut-off regions, the system generates nanoampere-level currents without requiring large-value resistors, thereby achieving precise current control with minimal chip area
Solution Approach 2:
The patent employs MOS tubes to generate their own leakage currents as the reference current source, eliminating the need for external resistor-based conversion circuits. The MOS tubes self-generate the required nanoampere-level currents through their intrinsic leakage characteristics when biased in specific operating regions, achieving both precision and area efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a low power consumption of 3.7 nW at room temperature, a temperature coefficient of 5.7 ppm/°C, and a compact chip area of 35 μm×18 μm, providing a stable reference voltage independent of temperature and process variations, suitable for wireless sensor networks and implantable biosensors.
Implementation Method 1
The NMOS tube working in the cut-off zone is used to generate an approximate exponential leakage current
Data Source
AI summary
The invention discloses a low power consumption and high precision resistance-free CMOS reference voltage source circuit, which includes a, a positive temperature coefficient voltage generation circuit and a starting circuit. The self-bias current source circuit uses two NMOS tubes with different threshold voltages in the subthreshold region to form a stack structure, which generates the bias current and negative temperature coefficient voltage on the order of nanoampere. The positive temperature coefficient voltage generation circuit uses PMOS differential to generate positive temperature coefficient voltage for the structure and performs first-order curvature compensation for negative temperature coefficient voltage.