Electric Variable Regulation TRIZ Cases

A high-voltage differential input stage and low-voltage gain stage improve reference accuracy while cutting area and level-shifting offset errors.

A common-gate error amplifier and loop gain stage help an NMOS LDO reject 10 MHz to 1 GHz supply noise with lower output ripple.

Multiple correction current cells are combined to flatten bandgap voltage drift across −60°C to 140°C and improve extreme-temperature compensation.

A GaN PTAT-CTAT reference scheme stabilizes regulated voltage against temperature drift while avoiding external reference parasitics.

Combining BJT and weak-inversion MOS temperature signals cancels bandgap curvature and delivers a more linear reference voltage or current.

Replica-column monitoring adjusts DLVR drive strength as Vin shifts, preserving loop stability without dynamic biasing losses.

Periodic voltage sampling replaces high-resistance biasing to cut bandgap power, area, and noise while keeping a stable output.

Monitored dropout voltage and replica-column Rds_on let a digital linear regulator stay stable across Vin changes without dynamic biasing.

Sense contacts on a single resistive track cancel contact resistance errors while counter-biasing a P-N junction for stable reference voltage.

A PTAT-CTAT MOSFET reference and feedback loop stabilize GaN voltage regulation while reducing temperature drift, line sensitivity, power, and area.

A cascode and low-amplitude clock keep chopper inputs below breakage threshold while cutting offset, noise, and drift in voltage references.

Phase advance compensation in the source-ground amplifier cuts Miller delay, improving load-transient response and phase margin.

Current feedback and class AB amplification cut overshoot and undershoot in linear power circuits while keeping output voltage stable.

A second depletion MOSFET and tuned resistor ratio counter temperature-driven Vref drift while keeping current consumption low.

A monitor transistor and cascode stage keep a capless regulator stable across wide input voltages while limiting power consumption.

A transistor switch and inverter path keeps mirror devices in deep reverse off state, reducing off-leak error and preserving current ratios.

Subthreshold and cut-off MOS leakage currents replace resistors and BJTs to stabilize reference voltage with low power and small chip area.

A CMOS reference voltage circuit uses saturation-region MOSFETs to cut line and process sensitivity while delivering stable low-voltage DC output.

Capacitor sampling and dynamic element matching stabilize band-gap reference voltage while reducing transistor mismatch and flicker noise.

Adaptive cascode biasing compensates temperature-driven current mismatch to keep reference voltage accurate across process, voltage, and temperature shifts.

Rotating active passgates each clock cycle spreads load current in a digital LDO, reducing electromigration stress and extending regulator life.

Combining PTAT voltage with two weakly correlated CTAT junction voltages reduces reference drift from temperature and process variation.

Adjusted current ratio between flipped-gate and non-flipped-gate transistors keeps reference voltage stable across temperature without BJT noise issues.

Zener bypassing and feedback paths cut heat and noise in bipolar high-voltage regulation while maintaining stable output for mass spectrometry.

An RC-delayed current feedback path stabilizes output voltage during load changes without sacrificing power supply frequency characteristics.

Selective switching of modular output stages cuts quiescent current in multi-mode IC voltage regulators without sacrificing needed current capability.

An accelerator circuit uses voltage differences to speed LDO settling during load changes without raising quiescent current or circuit area.

Subthreshold MOS and parasitic PNP devices enable one circuit to serve as a low-power bandgap reference and linear digital temperature sensor.

A current mirror and voltage-current conversion path stabilize reference current against supply and temperature fluctuations with a simple circuit.

A dual-mode control block lets the LDO regulate accurately from normal input levels down to near-dropout supply conditions while protecting circuits.

A dual-mode control block lets an LDO regulate accurately near dropout while avoiding damage across a wider supply voltage range.

A split main and auxiliary capacitor scheme pre-charges stored energy to cut LDO ripple, input noise, and external capacitor size.

Sub-threshold FDSOI curvature compensation stabilizes bandgap VREF at 0.8 V and below while correcting second-order temperature drift.

A scaling-amplifier feedback path lets one bandgap reference generate multiple output voltages while balancing flexibility, cost, and load variation.

A diode and limiting resistor block reverse current and preserve regulated voltage during supply glitches, avoiding brownout resets.

A configurable reverse-isolation path lets this series-shunt LDO balance high PSRR, ripple response, and lower power use.

Feedback and voltage-driving stages help this LDO hold output voltage with low headroom and fast response to load-current changes.

Monitored leakage current adjusts internal standby voltage to cut power loss while avoiding DPD delays and enabling fast recovery.

Delay-based tap prioritization coordinates parallel transformers to curb circulating reactive currents, stabilize voltage control, and reduce tap wear.

A load-dependent resistive device shifts the LDO zero to preserve phase margin across wide load currents without added quiescent current.

Dynamic Miller compensation shifts pole frequencies with load current, keeping capacitor-less LDOs stable and responsive without a large output capacitor.

Gradient tuning and level shifting flatten VCCHG temperature drift, keeping internal regulated voltage in range across IC operating temperatures.

A divided gate voltage below the MOS cross point cancels temperature drift, keeping reference current stable despite Fermi-level differences.

Isolating BJT collectors from the bandgap core cuts noise and substrate injection while keeping the reference voltage stable across temperature changes.

A startup and reference-detection circuit stabilizes bandgap voltage during slow input ramps, cutting power use while ensuring restart.

A gain limiter stage lowers LDO loop gain to preserve phase margin, improve static load regulation, and reduce output capacitance needs.

A divided gate voltage below the cross point offsets Vref temperature drift, keeping a MOS reference current stable across ambient changes.

A sensed pre-charge path biases the current mirror common node near steady state, cutting output current startup delay without added power.

A dual-input-stage error amplifier switches by reference voltage to avoid startup output jumps while preserving high PSRR in an LDO.

A hysteresis-controlled protection transistor stays off until a sense threshold is crossed, limiting fault current with less heat and power loss.