Reference Current Source Using Cross-Point Gate Voltage

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Solution Overview

Problem

Existing reference current sources face challenges in supplying stable reference currents against changes in ambient temperature due to temperature fluctuations affecting the reference voltage circuit, particularly when using transistors with different Fermi levels.

Innovation Solution

A reference current source design incorporating a reference voltage circuit with a depletion type MOS transistor and an enhancement type MOS transistor of the same conductivity type and impurity concentration but different Fermi levels, along with a voltage division circuit that outputs a divided voltage within a specific range to cancel temperature fluctuations, ensuring the output MOS transistor's drain current remains stable across temperature changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a reference voltage circuit uses transistors with different Fermi levels to improve manufacturing precision, then manufacturing variations are reduced, but temperature stability deteriorates due to temperature-dependent Fermi level differences

Engineering Contradiction:
Improvemanufacturing variationsVSAvoidtemperature stability
Core Design Contradiction:
Manufacturing precisionVSStability of the object's composition

Solution Approach 1:

The patent applies parameter changes by adjusting the gate voltage of the output MOS transistor to a specific value (cross point voltage) where the temperature coefficient of the drain current becomes zero. This parameter optimization allows the circuit to operate at a point where temperature variations do not affect the reference current, effectively canceling the temperature characteristic while maintaining the manufacturing precision benefits of using transistors with different Fermi levels

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If the gate voltage of the output MOS transistor is increased to improve reference current stability, then manufacturing variations are suppressed, but temperature sensitivity increases due to the voltage range exceeding the cross point

Engineering Contradiction:
Improvemanufacturing variationsVSAvoidtemperature sensitivity
Core Design Contradiction:
Manufacturing precisionVSTemperature

Solution Approach 1:

The patent precisely controls the gate voltage parameter to be at or below the cross point voltage, where the temperature coefficient of the MOS transistor drain current is zero. This parameter optimization simultaneously achieves manufacturing variation suppression through the transistor structure while eliminating temperature sensitivity by operating at the optimal voltage point

Inventive Principle:
Principle #35Parameter changes

3Stability of the object's composition

If a voltage division circuit is added to reduce current through the reference resistor to suppress reference current fluctuations, then reference current stability improves, but device complexity increases

Engineering Contradiction:
Improvereference current stabilityVSAvoidcircuit complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent achieves reference current stability by changing the operating parameter (gate voltage) of the existing output MOS transistor to the cross point voltage, rather than adding complex voltage division circuits. This parameter optimization approach suppresses reference current fluctuations due to both manufacturing variations and temperature changes while maintaining relatively simple circuit architecture

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively cancels the temperature characteristic of the reference voltage, allowing the reference current source to supply a stable reference current despite ambient temperature variations, by adjusting the gate voltage of the output MOS transistor to maintain a consistent drain current.

Implementation Method 1

an enhancement type MOS transistor having same conductivity type and impurity concentration as a channel of the depletion type MOS transistor and a different Fermi level from a gate electrode of the depletion type MOS transistor

Methodology Applied
Scientific EffectFermi level difference:

Implementation Method 2

a voltage division circuit, dividing the reference voltage and outputting a divided voltage

Methodology Applied
Scientific EffectVoltage division:

Implementation Method 3

the divided voltage is within a voltage range which is 0V or above and lower than a cross point at which a gate voltage-drain current characteristic of the output MOS transistor does not depend on temperature

Methodology Applied
Scientific EffectTemperature characteristic cancellation:

Data Source

PatentEP4379497A1Reference current source
Publication Date: 2024.06.05 ABLIC INC
  • EP4379497A1 patent drawingFigure 1
  • EP4379497A1 patent drawingFigure 2A
  • EP4379497A1 patent drawingFigure 2B

AI summary

A reference current source (100) includes a reference voltage circuit (110), generating a reference voltage (Vref); a voltage division circuit (130), dividing the reference voltage (Vref) and outputting a divided voltage (Vdiv); and an output MOS transistor (140), supplying a reference current (Iref) in response to the divided voltage (Vdiv) being applied to a gate terminal (140G). The reference voltage circuit (110) includes a depletion type MOS transistor (111), and an enhancement type MOS transistor (112) having same conductivity type and impurity concentration as a channel (111c) of the depletion type MOS transistor (111) and a different Fermi level from a gate electrode (111g) of the depletion type MOS transistor (111). The voltage division circuit (130) outputs the divided voltage (Vdiv) within a voltage range which is 0V or above and lower than a cross point (X) to the gate terminal (140G) of the output MOS transistor (140).