NMOS LDO Architecture for High-Frequency PSRR Improvement
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Solution Overview
Problem
Current low-dropout regulators (LDOs) with a cascaded flipped voltage follower (CAS-FVF) structure struggle to effectively reject digital noise in the high frequency band of 10 MHz to 1 GHz due to deteriorating power supply rejection ratio (PSRR), which is a bottleneck in meeting the noise rejection requirements of system-on-a-chip (SoC) designs for wireless communication.
Innovation Solution
The proposed solution involves a low-dropout regulator design using a first N-channel metal-oxide-semiconductor (NMOS) transistor as a power transistor, coupled with a common-gate error amplifier and a common-source loop gain amplifier, which isolates the supply voltage from the output voltage, reducing the small-signal gain and thereby improving PSRR in the high frequency band. Additionally, a second NMOS transistor is used to further isolate the supply voltage impact, and a low-pass filter can be included to filter high-frequency components from the supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a CAS-FVF structure LDO is used, then the LDO achieves low power, small area, and low noise, but the PSRR deteriorates in the high frequency band (10 MHz to 1 GHz)
Solution Approach 1:
The LDO is segmented into multiple functional modules: a power transistor stage, an error amplifier stage, and a loop gain amplifier stage. Each stage performs a specific function, allowing the PSRR to be optimized independently in the high frequency band while maintaining the overall low power and small area characteristics of the CAS-FVF structure.
Solution Approach 2:
A loop gain amplifier is introduced as an intermediary component between the error amplifier and the power transistor. This intermediary stage provides additional gain specifically in the high frequency band, improving PSRR without significantly increasing the overall device complexity or power consumption.
2Object-affected harmful factors
If the supply voltage is directly coupled to the output, then the LDO operates with low dropout voltage, but noise from the supply voltage directly impacts the output voltage
Solution Approach 1:
A feedback mechanism is implemented where the output voltage is sampled and compared with a reference voltage. The error amplifier generates a correction signal that is amplified by the loop gain amplifier and fed back to the power transistor gate, creating a negative feedback loop that actively compensates for supply voltage noise and maintains output stability.
Solution Approach 2:
The loop gain amplifier acts as an intermediary that decouples the supply voltage noise from the output. By providing additional gain in the feedback path, it reduces the small-signal gain from the supply voltage to the output, thereby improving noise rejection while maintaining the low dropout characteristic through the direct coupling path.
Data Source
AI summary
A low-dropout regulator includes a first power transistor, where the first power transistor is a first NMOS transistor, a drain of the first NMOS transistor is coupled to a power supply end, a source of the first NMOS transistor is configured to provide an output current for a load, and a gate of the first NMOS transistor is configured to receive a second feedback voltage; an error amplifier, where the error amplifier is a common-gate amplifier and is configured to generate a first feedback voltage based on an output voltage provided for the load and a reference voltage; and a loop gain amplifier, where the loop gain amplifier is a common-source amplifier and is configured to generate the second feedback voltage based on the first feedback voltage.