MOS Reference Current Source With Cross-Point Temperature Compensation

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Solution Overview

Problem

Existing reference current sources face challenges in supplying a stable reference current against changes in ambient temperature due to fluctuations in the reference voltage, particularly because the conductivity type and impurity concentration of transistors are the same but Fermi levels differ, leading to manufacturing variations and temperature sensitivity.

Innovation Solution

A reference current source incorporating a reference voltage circuit with a depletion type MOS transistor and an enhancement type MOS transistor of the same conductivity type and impurity concentration but different Fermi levels, where the reference voltage is divided and applied to an output MOS transistor with a gate voltage below a 'cross point' to ensure the drain current increases with temperature, thereby stabilizing the reference current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a reference voltage circuit uses transistors with the same conductivity type and impurity concentration but different Fermi levels, then manufacturing precision is improved, but temperature stability deteriorates

Engineering Contradiction:
Improvemanufacturing variationsVSAvoidtemperature stability
Core Design Contradiction:
Manufacturing precisionVSTemperature

Solution Approach 1:

The patent changes the gate voltage parameter of the output MOS transistor to operate below the cross point, where the drain current has a positive temperature coefficient. This parameter change compensates for the temperature instability introduced by using transistors with different Fermi levels, thereby maintaining temperature stability while achieving manufacturing precision.

Inventive Principle:
Principle #35Parameter changes

2Temperature

If the gate voltage of the output MOS transistor is set below the cross point, then temperature stability is improved, but the voltage range for operation is restricted

Engineering Contradiction:
Improvetemperature stabilityVSAvoidvoltage range
Core Design Contradiction:
TemperatureVSAdaptability or versatility

Solution Approach 1:

The patent performs preliminary action by pre-determining the optimal gate voltage range below the cross point during the design phase. The voltage division circuit is configured in advance to provide the appropriate divided voltage within this restricted range, ensuring temperature stability while maintaining sufficient adaptability for practical applications.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the reference voltage is divided and applied to the gate terminal, then the reference current stability is improved, but the circuit complexity increases

Engineering Contradiction:
Improvereference current stabilityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a voltage division circuit as an intermediary component between the reference voltage source and the output MOS transistor gate terminal. This intermediary divides the reference voltage to provide the appropriate gate voltage, improving reference current stability while adding only moderate circuit complexity through simple resistive division.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240176379A1Reference current source
Publication Date: 2024.05.30 ABLIC INC
  • US20240176379A1 patent drawing
  • US20240176379A1 patent drawing
  • US20240176379A1 patent drawing

AI summary

A reference current source 100 includes a reference voltage circuit 110, generating a reference voltage Vref; a voltage division circuit 130, dividing the reference voltage Vref and outputting a divided voltage Vdiv; and an output MOS transistor 140, supplying a reference current Iref in response to the divided voltage Vdiv being applied to a gate terminal 140G. The reference voltage circuit 110 includes a depletion type MOS transistor 111, and an enhancement type MOS transistor 112 having same conductivity type and impurity concentration as a channel 111c of the depletion type MOS transistor 111 and a different Fermi level from a gate electrode 111g of the depletion type MOS transistor 111. The voltage division circuit 130 outputs the divided voltage Vdiv within a voltage range which is 0V or above and lower than a cross point X to the gate terminal 140G of the output MOS transistor 140.