CMOS Unit With Segmented Gates For Speed And Power
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Solution Overview
Problem
MOSFET technologies face a tradeoff between high speed and low power consumption, where optimizing one criterion often negatively impacts the other, making it challenging to design mobile products that require both high speed and low power usage.
Innovation Solution
The use of a pair of high threshold voltage (HTV) and low threshold voltage (LTV) CMOS transistors, where HTV transistors are configured to operate in a stand-by mode to reduce leakage and LTV transistors operate at high speed, with both types of transistors being isolated from the substrate and laterally dielectrically isolated from each other, allowing for efficient power management and high-speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low threshold voltage is used to increase switching speed, then speed is improved, but off-state leakage increases leading to higher power consumption
Solution Approach 1:
The transistor gate is segmented into two independent gates (first gate and second gate) that can be controlled separately. This allows independent optimization of different transistor states: one gate controls threshold voltage for speed while the other manages leakage for power consumption
Solution Approach 2:
The transistor operates with dynamically adjustable threshold voltage through dual gate control. The first gate establishes a base threshold while the second gate can dynamically adjust the effective threshold voltage to optimize performance for different operating conditions (high speed vs. low power modes)
2Loss of energy
If high threshold voltage is used to reduce off-state leakage and lower power consumption, then power consumption is reduced, but switching speed decreases
Solution Approach 1:
The transistor gate is segmented into two independent gates (first gate and second gate) that can be controlled separately. This allows independent optimization of different transistor states: one gate controls threshold voltage for speed while the other manages leakage for power consumption
Solution Approach 2:
The transistor operates with dynamically adjustable threshold voltage through dual gate control. The first gate establishes a base threshold while the second gate can dynamically adjust the effective threshold voltage to optimize performance for different operating conditions (high speed vs. low power modes)
3Device complexity
If transistors are not isolated from substrate, then device complexity is reduced, but substrate noise and interference increase affecting circuit performance
Solution Approach 1:
The transistor channel is extracted from direct contact with the substrate by forming it in a well structure (n-well for PMOS, p-well for NMOS). This isolates the active channel region from the substrate, reducing substrate noise and interference while maintaining manageable device complexity through standard well formation processes
Data Source
AI summary
A semiconductor device 100 has N-well regions 18 holding PMOS devices 110, 112 and P-type regions 14 holding NMOS devices 114, 116. Devices 110 and 114 have high thresholds and devices 112 and 116 have low thresholds. The PMOS devices are junction isolated from the substrate 10 by the N-well 18 and the NMOS devices are isolated from the substrate by the N-type layer 13. Field oxide regions 20 laterally isolate the PMOS from the NMOS devices. The high threshold CMOS devices 110, 114 connect the low threshold CMOS devices to opposite rails Vdd and Vss. A control terminal 121 turns the high threshold devices on to let the low threshold devices switch rapidly. In stand-by mode, the high threshold devices are off and there is very low leakage current.