CMOS Image Sensor FD Connection Structure for Lower Capacitance
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Solution Overview
Problem
In CMOS image sensors, the sharing of a predetermined transistor among multiple pixels leads to increased floating diffusion (FD) capacity due to long wiring lengths, resulting in degraded conversion efficiency and a deteriorated signal-to-noise (S/N) ratio.
Innovation Solution
The implementation of a trench structure between pixels, with a connection portion that contacts both pixels and the trench, allows for electrical connection of FD areas without increasing FD capacity, thereby improving conversion efficiency and S/N ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a predetermined transistor is shared by a plurality of pixels and FD areas are connected using wirings, then device complexity is reduced, but wire length increases causing FD capacity to increase and S/N ratio to deteriorate
Solution Approach 1:
The patent introduces a vertical dimension by forming a via hole that penetrates through the insulating film to connect FD areas. This vertical connection path replaces the conventional horizontal wiring approach, effectively reducing the connection length and FD capacity while maintaining the shared transistor configuration for device complexity reduction.
2Reliability
If a large contact or large FD area is formed to connect FD areas and tolerate misalignment, then electrical connectivity is improved, but device area increases and conversion efficiency decreases
Solution Approach 1:
The patent changes the geometric parameters of the contact structure by forming a via hole with specific dimensions (width of 0.5-2.0 μm, depth penetrating through the insulating film). This precise parameter control enables reliable electrical connection with minimal area occupation, improving conversion efficiency while maintaining connectivity.
Solution Approach 2:
The insulating film with via hole acts as an intermediary structure that enables electrical connection between FD areas without requiring large contact areas. The via hole provides a focused connection path that reduces the need for large FD areas, thereby improving conversion efficiency while ensuring electrical connectivity.
3Productivity
If wiring length is reduced to decrease FD capacity, then conversion efficiency is improved, but device complexity increases
Solution Approach 1:
The patent reduces wiring length by transitioning from horizontal wiring to vertical via hole connection. This dimensional change creates a more direct connection path between FD areas, significantly reducing the effective connection length and improving conversion efficiency without substantially increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the S/N ratio by reducing FD capacity and improving conversion efficiency while maintaining efficient electrical connectivity between shared pixels.
Implementation Method 1
a photodiode and a transistor in each pixel
Data Source
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AI summary
The present technology relates to an image sensor and an electronic device that can reduce an FD capacity. An image sensor includes a substrate, a first pixel including a first photoelectric conversion area provided in the substrate, a second pixel including a second photoelectric conversion area adjacent to the first photoelectric conversion area and provided in the substrate, a trench provided in the substrate between the first photoelectric conversion area and the second photoelectric conversion area, a first area included in the first pixel, a second area included in the second pixel, and a third area in contact with the first area, the second area, and the trench. The present technology can be applied to, for example, a CMOS image sensor.