CMOS Image Sensor Layout for Higher Pixel Fill Factor
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Solution Overview
Problem
Traditional CMOS imaging sensors have a reduced fill factor due to the circuit device region occupying space that could be used for photosensitive areas, affecting the photosensitive effect of pixels.
Innovation Solution
A CMOS imaging sensor structure is designed with a circuit device region on the frontside of a semiconductor substrate and a first photosensitive region below it, isolated by a buried oxygen layer and connected through a conductive trench, utilizing a SOI substrate with epitaxial and silicon layers to optimize space usage and improve fill factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the circuit device region and photosensitive region are arranged side by side in a horizontal direction, then the circuit device can be formed using traditional CMOS processes, but the fill factor of the pixels is reduced
Solution Approach 1:
The patent transitions from a two-dimensional horizontal arrangement to a three-dimensional vertical stacking configuration. The circuit device region is positioned on the front surface while the photosensitive region is positioned on the back surface of the semiconductor substrate, connected via conductive structures (through-silicon holes or trench isolation structures). This spatial reconfiguration allows both regions to occupy different layers, eliminating the area conflict that limits fill factor in planar designs while maintaining CMOS process compatibility.
2Adaptability or versatility
If the circuit device region occupies a part of the pixel area, then the circuit functions can be integrated, but the photosensitive effect is influenced
Solution Approach 1:
The patent segments the pixel structure into distinct functional regions positioned in different spatial locations: the circuit device region on the front surface and the photosensitive region on the back surface. This segmentation is enabled by introducing isolation structures (trench isolation or through-silicon holes) that physically separate the two regions. By dividing the pixel into stacked functional modules, the circuit integration function is preserved while the photosensitive region is freed from circuit area constraints, improving photosensitive effectiveness.
3Area of moving object
If a vertical stacked structure is used to increase fill factor, then the photosensitive area is increased, but the manufacturing complexity increases
Solution Approach 1:
The patent introduces intermediary structures to facilitate the vertical stacked configuration: conductive structures (through-silicon holes filled with conductive material or trench isolation structures with conductive plugs) serve as mediators to electrically connect the circuit devices on the front surface with the photosensitive region on the back surface. These intermediary elements, while adding some manufacturing steps, use standard CMOS-compatible processes and simplify the overall fabrication compared to alternative complex 3D integration techniques, thereby achieving increased photosensitive area with controlled manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design increases the fill factor of the photosensitive region, allows for more optimized circuit design without area restrictions, and enhances overall chip performance by forming a larger photosensitive area while being compatible with standard CMOS processes, reducing production difficulty and costs.
Implementation Method 1
the circuit device region is isolated from the first photosensitive region by an isolation region
Implementation Method 2
the circuit device region is electrical connected with the first photosensitive region through a conductive trench
Implementation Method 3
the photosensitive region is used for receiving external lights and generating an electrical signal
Data Source
AI summary
A CMOS imaging sensor structure and a manufacturing method therefor. The CMOS imaging sensor structure comprises a pixel unit of the CMOS imaging sensor set on a semiconductor substrate, the pixel unit comprises a circuit device region and a first photosensitive region, the circuit device region is set on the frontside of the semiconductor substrate, the first photosensitive region is set correspondingly in the semiconductor substrate below the circuit device region, the circuit device region is isolated from the first photosensitive region by an isolation region, and the circuit device region is electrical connected with the first photosensitive region through a conductive trench, a fill factor of a photosensitive region is increased, and performances of a reading circuit is increased by a more optimized design scheme. A second photosensitive region of the pixel unit can also be set on the semiconductor substrate on a side of the circuit device region, thus a larger photosensitive region can be formed together with the first photosensitive region. The present invention also provides a manufacturing method for the CMOS imaging sensor structure.