Multi-Bank CMOS Image Sensor Sampling for Noise-Aware Single-ADC Readout
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Solution Overview
Problem
Existing multi-input CMOS image sensor processor systems face challenges with high cost, inaccurate analog-to-digital conversion due to external noise, and high power consumption, particularly because they require multiple sample/hold circuits and ADCs, which also lead to inefficiencies in imaging speed and channel gain mismatch.
Innovation Solution
The system employs a single ADC for multiple CMOS image sensors by using out-of-phase clock signals to enable parallel sampling, with adjustable clock edge phases to avoid noise interference and allow for self-calibration, reducing the need for multiple sample/hold circuits and ADCs, and optimizing sampling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple ADCs and sample/hold circuits are used for each CMOS sensor, then conversion accuracy is maintained, but power consumption increases and system cost increases
Solution Approach 1:
Multiple ADCs and sample/hold circuits are merged into a single shared ADC and sample/hold circuit that serves all CMOS sensors. The system multiplexes the single ADC across multiple sensor channels, allowing accurate conversion while reducing power consumption and component count.
Solution Approach 2:
A single ADC and sample/hold circuit is designed to universally serve multiple CMOS sensor channels. The circuit performs analog-to-digital conversion for different sensor banks sequentially, making one component perform the function of what would traditionally require multiple dedicated components.
2Measurement precision
If multiple ADCs and sample/hold circuits are used for each CMOS sensor, then conversion accuracy is maintained, but device complexity increases
Solution Approach 1:
Multiple ADCs and sample/hold circuits are merged into a single shared ADC and sample/hold circuit that serves all CMOS sensors. The system multiplexes the single ADC across multiple sensor channels, allowing accurate conversion while reducing power consumption and component count.
Solution Approach 2:
A single ADC and sample/hold circuit is designed to universally serve multiple CMOS sensor channels. The circuit performs analog-to-digital conversion for different sensor banks sequentially, making one component perform the function of what would traditionally require multiple dedicated components.
3Use of energy by moving object
If a single ADC is used for multiple CMOS sensors, then power consumption is reduced and cost is reduced, but analog-to-digital conversion accuracy deteriorates due to external noise
Solution Approach 1:
The system segments CMOS sensors into different banks that are sampled at different times. The single ADC converts signals from one bank at a time, isolating each conversion process from noise generated by other banks. This temporal segmentation prevents noise interference while maintaining the benefits of a single ADC.
Solution Approach 2:
The system uses periodic sampling where different banks of CMOS sensors are activated and sampled alternately in time. This periodic action ensures that when one bank is being converted, other banks are inactive, preventing noise interference and maintaining conversion accuracy with a single ADC.
4Measurement precision
If multiple ADCs are used, then conversion accuracy is maintained, but imaging speed decreases due to serial processing
Solution Approach 1:
The system segments CMOS sensors into different banks that are sampled at different times. The single ADC converts signals from one bank at a time, isolating each conversion process from noise generated by other banks. This temporal segmentation prevents noise interference while maintaining the benefits of a single ADC.
Solution Approach 2:
The system uses periodic sampling where different banks of CMOS sensors are activated and sampled alternately in time. This periodic action ensures that when one bank is being converted, other banks are inactive, preventing noise interference and maintaining conversion accuracy with a single ADC.
5Reliability
If multiple sample/hold circuits are used, then each sensor can be processed independently, but system cost increases
Solution Approach 1:
Multiple ADCs and sample/hold circuits are merged into a single shared ADC and sample/hold circuit that serves all CMOS sensors. The system multiplexes the single ADC across multiple sensor channels, allowing accurate conversion while reducing power consumption and component count.
Data Source
AI summary
A CMOS image sensor system includes first and second groups of CMOS sensors each responsive to periodic first and second clock signal edges, the second clock signal edge being out-of-phase with the first clock signal edge. Output signals of the first group of CMOS sensors are coupled to a first group of sampling capacitors, respectively, by a first group of sampling switches. Then output signals of the second group of CMOS sensors are coupled to a second group of sampling capacitors, respectively, by means of a second group of sampling switches. Sampled signals on the second group of sampling capacitors to an input of an ADC, and then sampled signals on the first group of sampling capacitors are coupled to the input of the ADC by means of by multiplexing and sample/hold circuitry. A phase of at least one of the first and second clock signal edges is adjusted in response to calibration information so as to avoid circuit noise from being superimposed on sampled signals coupled to the input of the ADC.