CMOS Image Sensor Superlattices Reduce Crosstalk
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Solution Overview
Problem
Current semiconductor devices, such as CMOS image sensors, face limitations in charge carrier mobility and crosstalk between adjacent pixels, which can be enhanced by advanced materials and processing techniques.
Innovation Solution
The integration of semiconductor substrates with retrograde wells and superlattices, comprising stacked groups of semiconductor and non-semiconductor monolayers, which reduce effective mass and enhance mobility, and the use of shallow trench isolation regions and microlenses to minimize crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor structures are used, then manufacturing is simpler, but charge carrier mobility is limited
Solution Approach 1:
The patent employs composite material structures including superlattices with alternating layers of different semiconductor materials (e.g., SiGe/Si) and non-semiconductor monolayers (e.g., oxygen, carbon, nitrogen). These composite structures create strained band configurations that enhance charge carrier mobility while maintaining manufacturability through established epitaxial growth techniques.
Solution Approach 2:
The patent modifies material parameters by introducing strained semiconductor layers with controlled composition ratios (e.g., Si1-xGex where x is between 0.01 and 0.5). The strain engineering changes the effective mass and band structure parameters, thereby improving charge carrier mobility without requiring complete structural redesign.
2Productivity
If photodiodes are placed close together to increase pixel density, then productivity increases, but crosstalk between adjacent pixels increases
Solution Approach 1:
The patent introduces intermediate barrier layers and isolation structures between adjacent photodiodes. These intermediary elements include doped semiconductor layers and dielectric materials that act as potential barriers to prevent carrier diffusion and optical crosstalk between neighboring pixels, enabling higher pixel density without sacrificing signal isolation.
Solution Approach 2:
The patent applies different material compositions and doping profiles locally around each photodiode region. The superlattice structures have spatially varying compositions that create localized potential wells and barriers, providing tailored electrical and optical properties at each pixel location to minimize crosstalk while maintaining high density.
3Speed
If superlattices with multiple monolayers are integrated, then mobility enhancement improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the superlattice structure into segmented repeating units of thin monolayers (e.g., 1-10 nm thickness). Each segment is designed with specific thickness ratios to achieve the desired strain and band structure effects. This segmentation allows precise control through modular fabrication processes and reduces the cumulative tolerance accumulation problem.
Solution Approach 2:
The patent replaces mechanical thickness control methods with self-organizing epitaxial growth processes. The superlattice structures utilize self-assembled monolayers and strain-driven mechanisms that automatically achieve atomic-layer precision during growth, reducing reliance on external mechanical positioning and thickness control equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves charge carrier mobility and reduces crosstalk between pixels, leading to enhanced performance in CMOS image sensors by lowering conductivity effective mass and providing improved energy band structures and reduced scattering effects.
Implementation Method 1
Each of the first and second superlattices may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions
Implementation Method 2
The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices
Implementation Method 3
Each photodiode may include a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type
Implementation Method 4
A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent photodiodes formed in the substrate
Data Source
AI summary
A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent photodiodes formed in the substrate. Each photodiode may include a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the second conductivity type, and a second well within the retrograde well having the first conductivity type. Each photodiode may further include first and second superlattices respectively overlying each of the first and second wells. Each of the first and second superlattices may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.