CMOS Single Photon Avalanche Diode Deep Well Design
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Solution Overview
Problem
In CMOS technologies beyond the 0.25-μm node, there is no obvious method to form a low-noise Single Photon Avalanche Diode (SPAD) without specialized implants, which are costly and complex, and existing structures suffer from high dark count rates due to tunneling and stress-induced leakage currents.
Innovation Solution
A CMOS single photon avalanche diode with a breakdown region and guard ring formed in the epitaxial layer, utilizing a deep well implant with a lower doping concentration than conventional shallower implants, and a guard ring formed in the upper, lower-doped region of a retrograde well, without additional shallow implants, to extend the depletion region and reduce edge effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional shallow well implants are used to form the p-n junction, then the device can be manufactured using standard CMOS processes, but the depletion region is narrow causing high tunneling current and high dark count rates
Solution Approach 1:
The patent changes the doping concentration parameter by using a deep well implant with lower doping concentration (e.g., 1e16 to 1e18 atoms/cm³) compared to conventional shallow implants. This parameter change extends the depletion region width, reducing tunneling current and dark count rates while maintaining compatibility with CMOS fabrication processes.
Solution Approach 2:
The patent transitions from shallow lateral implants to a deep vertical well implant structure. This dimensional change in the implant depth allows the depletion region to extend deeper into the substrate, increasing the breakdown voltage and reducing edge effects that cause high dark counts in planar structures.
2Reliability
If high doping concentration implants are used, then the p-n junction can be formed effectively for avalanche breakdown, but the depletion region becomes narrow resulting in significant tunneling-induced carriers
Solution Approach 1:
The patent optimizes the doping concentration parameter by using lower doping levels (1e16 to 1e18 atoms/cm³) in the deep well implant compared to conventional high doping levels. This creates a wider depletion region that reduces tunneling probability while maintaining sufficient field strength for avalanche multiplication at the breakdown region.
Solution Approach 2:
The patent applies different doping concentrations to different regions: the deep well has lower doping for extended depletion region, while the breakdown region at the p-n junction interface maintains higher field strength for avalanche effect. This local quality differentiation optimizes both dark count reduction and detection efficiency.
3Reliability
If guard ring structures are added to prevent edge breakdown, then device reliability improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the guard ring function from a separate structural element and integrates it into the deep well implant itself. The deep well naturally forms a rounded depletion region that prevents edge breakdown without requiring additional guard ring implants or structures, thereby reducing device complexity while maintaining reliability.
Solution Approach 2:
The patent merges the deep well implant with the guard ring function. The deep well structure simultaneously serves as both the avalanche breakdown region and the edge protection mechanism, eliminating the need for separate guard ring structures and simplifying the overall device architecture.
4Object-generated harmful factors
If specialized implants are used to reduce dark count, then dark count rate decreases, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent makes the deep well implant serve multiple functions: it creates the avalanche breakdown region, extends the depletion region to reduce tunneling, provides edge protection against breakdown, and reduces dark count rates. This multi-functionality eliminates the need for specialized separate implants or processes, keeping manufacturing costs low while achieving excellent dark count performance.
Solution Approach 2:
The deep well implant structure is self-configuring to provide optimal performance. The rounded depletion region naturally forms to prevent edge breakdown, and the extended depletion width automatically reduces tunneling current. No additional specialized processing steps are required - the structure serves itself to reduce dark counts while maintaining manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a significant reduction in dark count rates, maintaining low noise levels while being manufacturable using existing CMOS processes, with photon detection efficiency exceeding 30% and viable for various applications, including medical and optical imaging.
Implementation Method 1
The avalanche process in solid-state devices has been known for at least fifty years, as has its application to photo-multiplication. An avalanche is triggered when reverse biasing a PN junction to around the breakdown voltage.
Implementation Method 2
The dark count mechanism has switched to tunneling in CMOS technologies from the 0.18-μm node onwards. The high doping concentration levels cause a very narrow depletion region resulting in a significant number of tunneling-induced carriers and increased dark count.
Data Source
AI summary
A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.