CMOS SPAD Pixel Guard Ring Design for Dark Count Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing single-photon avalanche photodiode (SPAD) technologies face challenges in forming high-density arrays using standard CMOS processes, as they suffer from high dark counts and reliability issues, limiting their application in low-light level sensing due to edge effects and material interface problems.

Innovation Solution

A design for an avalanche photodiode with a substrate of a first conductivity type, including a heavily doped region forming an avalanche multiplication region, a guard ring, and an outer well ring, which minimizes edge effects and dark counts by proper doping and structural design, allowing for integration into high-density arrays using standard deep submicron and nano CMOS processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If high voltage CMOS processes are used to manufacture SPADs, then single-photon detection capability is achieved, but reliability issues and high dark counts limit the technology to non-competitive feature sizes

Engineering Contradiction:
Improvesingle-photon detection capabilityVSAvoiddark count rate
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies local quality by implementing a multi-layer doping structure with specific regions having different doping concentrations. The multiplication region uses high doping concentrations to achieve low breakdown voltage, while guard rings and isolation regions use different doping levels to suppress edge effects and reduce dark counts, allowing standard CMOS processes to produce reliable SPADs

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes physical parameters by optimizing doping concentrations, junction depths, and geometric dimensions of the photodiode structure. By carefully controlling these parameters in standard CMOS processes, the patent achieves low breakdown voltage multiplication regions while maintaining low dark counts through proper guard ring design and isolation structures

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If standard CMOS processes are used for SPAD fabrication, then manufacturing simplicity is improved, but edge effects and material interface problems cause high dark counts

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoiddark counts from edge effects
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent introduces intermediary structures including guard rings and isolation regions that act as mediators between the multiplication region and the surrounding structures. These intermediary elements buffer edge effects and prevent premature breakdown at junction edges, reducing dark counts while maintaining compatibility with standard CMOS fabrication processes

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the photodiode structure into distinct functional regions with different doping profiles: a high-doping multiplication region, guard rings with intermediate doping, and isolation regions. This segmentation allows each region to be optimized for its specific function while being fabricated using standard CMOS processes

Inventive Principle:
Principle #1Segmentation

3Quantity of substance

If deep submicron and nano CMOS processes are used, then device density is improved, but ensuring low breakdown voltage and preventing latch-up becomes more difficult

Engineering Contradiction:
Improvedevice densityVSAvoidlatch-up prevention
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies local quality by implementing depth-selective doping in vertical junctions, where different doping concentrations are applied at different depths within the device structure. This allows the formation of low breakdown voltage multiplication regions while maintaining high-density integration and preventing latch-up through proper doping profiles in deep submicron and nano CMOS processes

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables the creation of high-density SPAD arrays with minimal dark counts, suitable for low-light level sensing, and allows for operation in both single-photon counting and digital modes, providing an infinite dynamic range and improved reliability.

Implementation Method 1

An avalanche photodiode can be made to detect single photons when operated above its breakdown voltage in what is known as Geiger mode in which a single incident photon can trigger an 'infinite' amount of photocurrent

Methodology Applied
Scientific EffectAvalanche breakdown: Avalanche Breakdown

Implementation Method 2

Optical sensors for extreme low-level light conditions can convert single photons into a measurable electrical signal

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS8259293B2Deep submicron and nano CMOS single photon photodetector pixel with event based circuits for readout data-rate reduction communication system
Publication Date: 2012.09.04 JOHNS HOPKINS UNIVERSITY
  • US8259293B2 patent drawing
  • US8259293B2 patent drawing
  • US8259293B2 patent drawing

AI summary

An avalanche photodiode is disclosed. The avalanche photodiode includes a substrate of a first conductivity type. A first well of a second conductivity type is formed within the substrate. A second well of the second conductivity type is formed substantially overlying and extending into the first well. A heavily doped region of the first conductivity type is formed substantially overlying and extending into the first well, the junction between the heavily doped region and the second well forming an avalanche multiplication region. A guard ring is formed from a first conductivity material positioned substantially about the periphery of the multiplication region at least partially underlying the heavily doped region. An outer well ring of the second conductivity type is formed about the perimeter of the deep well and the guard ring.